Challenges are our drive, innovation our calling. We at Kandou are a team of passionate accomplished professionals making a mark in the semiconductor industry. We're an innovative leader in high-speed and energy efficient chip-chip link solutions critical to the evolution of the electronics industry, continuously developing to meet the demands of not just the customers of today, but of tomorrow too. If you love to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you.
We are actively seeking a resourceful Physical Design Engineer Digital & STA Timing, based in either Lausanne, Switzerland, UK (Reading/Northampton), Germany (Dortmund), or Denmark.
Key Responsibilities
- As a Physical Design Engineer, you will work closely with the Architecture, RTL, DFT and Manufacturing teams to ensure first-time-right high-volume silicon production
- Timing Constraints development, timing constraints validation, signoff Static Timing Analysis and full chip & block-level timing closure
- Block and chip level STA with all aspects, reviewing and defining constraints with the design team, implementing SDC constraints to be used for block and chip (flat) STA, analyze violations and clean with help of frontend design and PD team
- Synthesis, UPF development, floor-planning, power grid design, place & route, clock tree synthesis, electromigration / IR-Drop analysis, power/signal integrity analysis, Crosstalk analysis, formal equivalence checking and physical verification (DRC / LVS / Antenna)
- Participate in developing improvements to scripts/methodologies/flows
- Interact closely with the design team to understand requirements and implement solutions for STA as also helping on providing design views for use with digital PD flows (LIB, LEF, DEF, GDS, SPEF, etc.)
- Support IP and chip level integration
- Support and interact with customers on requirements and IP delivery
- Manage workload and schedule and report to internal management team
Skills
- Self-motivated, with strong sense of ownership and responsibility. Good communicator and team player
- Good understanding of RTL to GDS implementation flow (synthesis, P&R, LEC, PV & STA)
- Good scripting capabilities (shell, TCL, Python, make) and good understanding of data management (revision control system)
- Experience in gathering and defining SDC constraints, specifically on top-level incl. DFT. Requires great team-work, tenacity, stamina and eye-for-detail. Also requires excellent communication and people skills to pull information from team members.
- Flow development with focus on cross project reusability
Experience
- 10+ years’ experience in the semiconductor industry, with min. 5 years in a digital Physical Design technical leadership role
- Experience on modern semiconductor process technologies including 14/16nm, 7nm, 5nm & 3nm
- Experienced user of EDA tools for design and verification such as, Cadence Genus and Innovus, LEC, Calibre/PVS DRC/LVS, parasitics extraction, EM, and IR drop, ESD, etc.
- Expertise in Timing Constraints and Static Timing Analysis (STA)
- Expertise in Timing/SDC constraints generation and management
- Experience in SDC verification tools – such as Synopys TCM
- Expertise in running hierarchical and flat static timing analysis incl. cross talk SI/glitch analysis
- Experience in CPF/UPF technologies and flows is highly desirable
- Exposure to flip-chip package technologies and wire bond package technologies
- Experience in hierarchical floor planning and implementation
- Experience in release management and tape out procedures
- Experience in library setup and flow development with focus on cross project reusability
- Experience in DFT methodologies and implementation schemes
Education
- Bachelors/Masters of Engineering in Electronics and Electrical Engineering/Computer Science (equivalent or higher)
If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would really love to hear from you. Together We Kandou It !
Visit us at www.kandou.ai and https://www.linkedin.com/company/kandou-ai/
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What We Do
Founded in 2011, Kandou is the innovative leader in high-speed, energy efficient, chip-to-chip link solutions critical to the evolution of the electronics industry. Kandou enables a better-connected world by offering disruptive technology through licensing and standard products that empower the devices we use every day to become smaller, more energy efficient and more cost effective. Kandou has a strong IP portfolio that includes Chord™ signaling, which has been adopted into industry specifications by JEDEC and the OIF. These innovations and implementations deliver a fundamental advance in interconnect technology that lowers the power consumed and improves the performance of chip links, unlocking new capabilities for customer devices and systems. Kandou is a fabless semiconductor company headquartered in Lausanne, Switzerland with offices in Europe, North America and Asia.
