Physical Design (Backend) Technical Leader

Reposted One Month Ago
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Petah Tikva, ISR
In-Office
Expert/Leader
Artificial Intelligence • Cloud • Information Technology • Software
Creating world-changing technology that enriches the lives of every person on earth.
The Role
Lead backend implementation of advanced Intel wireless products, optimize designs, mentor juniors, and collaborate with teams to enhance VLSI designs.
Summary Generated by Built In
Job Details:

Job Description: 

We are seeking for a highly experienced and motivated Senior Physical Design Technical Lead to join our group and lead and drive backend implementation of advanced Intel wireless products.
As part of your job you will define and improve design implementation flows, automation and signoff methodologies.
Technically Lead the physical design flow and implementation activities for complex VLSI chips, ensuring high performance and reliability.
Optimize power, performance, and area (PPA) metrics through advanced techniques and tools.
Analyze and resolve design issues related to Place and Route, timing, power, signal integrity, and manufacturability.
Collaborate with other Intel design teams to ensure seamless integration and optimization of design specifications.
Mentor and guide junior engineers, providing technical expertise and support. Interface with EDA vendors to evaluate and integrate new tools and technologies and stay updated with the latest industry trends and advancements in VLSI Physical design.

Qualifications:
  • BSc/MSc in electrical or computer engineering.
  • 10+ years of hands-on experience in VLSI physical design, with a proven track record of successful projects working with advanced technology nodes.
  • Excellent familiarity with all Physical Design implementation flows and techniques, including floorplanning, placement, routing, and timing closure.
  • Proficiency in Synopsys EDA tools (Cadence is an advantage).
  • Knowledge of scripting languages such as Python, Perl, or TCL.
  • Strong understanding of STA, IR drop, EM analysis, DRC/LVS, and ECO flows. Experience with power, performance, and area (PPA) optimization.
  • Experience in managing and mentoring technical teams.
  • Excellent problem-solving skills and attention to detail. Strong communication and teamwork skills

          

Job Type:Experienced Hire

Shift:Shift 1 (Israel)

Primary Location: Israel, Petah-Tikva

Additional Locations:

Business group:The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

*

Skills Required

  • BSc/MSc in electrical or computer engineering
  • 10+ years of hands-on experience in VLSI physical design
  • Excellent familiarity with all Physical Design implementation flows and techniques
  • Proficiency in Synopsys EDA tools
  • Knowledge of scripting languages such as Python, Perl, or TCL
  • Strong understanding of STA, IR drop, EM analysis, DRC/LVS, and ECO flows
  • Experience in managing and mentoring technical teams
  • Excellent problem-solving skills and attention to detail

Intel Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.

  • Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
  • Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
  • Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.

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The Company
HQ: Santa Clara, CA
75,000 Employees
Year Founded: 1968

What We Do

Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside. With more ingenuity and creativity inside, our work is at the heart of countless innovations. From major breakthroughs to things that make everyday life better— they’re all powered by Intel technology. With a career at Intel, you can help make the future more wonderful for everyone.

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