PDK Software Engineer - VLSI Physical Verification

Job Details:

Job Description: Designs, implements, verifies, and supports the enablement and adoption of hardware design tools, flows, and methodologies. Defines methodologies for hardware development related to technology node and EDA tool enabling. Creates and verifies unique hardware designs, assembles design platforms, and integrates components into hierarchical systems to provide deployment coverage for endtoend EDA tool testing on new technology nodes. Develops, tests, and analyzes engineering design automation tools, flow, and methodologies to improve efficiency and optimize power and performance. Supports development and enhancement of platforms, databases, scripts, and tools flows for design automation. Builds deep understanding of digital design, verification, structural and physical layout, fullchip integration, power and performance, clocking, and/or timing to enhance future TFM development. Collaborates with EDA vendors on defining and early testing of nextgeneration design tools.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Bachelor of Science in Computer Engineering (CE), Electrical Engineering (EE) with 3+ years of semiconductor industry experience OR Master of Science in CE, EE with 1+ years of semiconductor industry experience.
• Required semiconductor industry experience in the following areas:
  • DRC or LVS runsets development in any one of the EDA tools (Synopsys ICV, Siemens/Mentor Calibre, and Cadence Pegasus)
  • Unix/Linux operating system
  • At least one of the following: C++, Python, Perl, TCL
  • At least one of the following: VLSI design process, reliability verification, ESD concepts, standard cell library, and memory architectures

Preferred Qualifications:

• Knowledge in semiconductor device physics, models, parasitic extraction, and technology scaling
• Experience with working in software repository management tools like Git

          

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, Oregon, Hillsboro

Additional Locations:US, California, Folsom, US, Texas, Austin

Business group:As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$126,420.00-$178,480.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.