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The Role
Supports Intel Ethernet products across discrete controllers and integrated SoC Ethernet IP. Diagnoses complex board, system, PCIe, and Ethernet interlink issues; resolves customer problems; develops and validates debug tools with software teams; and supports product development from hardware design through mass production. Requires independent problem solving, customer management, high-speed I/O debugging, lab equipment expertise, and collaboration across engineering teams. Some travel may be required.
Summary Generated by Built In
Job Details:Job Description: The Customer Experience and Support (CES) team within CEG NSG group is looking for a talented senior Network Systems and Solutions Engineer to support Intel Ethernet products. The primary job role is technical enabling of Intel Ethernet product for both discrete Ethernet controller and integrated Ethernet IP on SOC. This includes technical debug and issue resolution of complex issues on board design, system-level applications, PCIe interlink, and Ethernet interlink. The role is also expected to work independently on resolving customer issues and drive resolution as delivery.
The role will be expected to collaborate software developer to accomplish debug tool development and validation. Complex issue debug, problem solving, multi-tasking, organization, and customer management skills are critical to success in this role. Some travel may be required as appropriate based on customer needs.Qualifications:Minimum Qualifications:
- Bachelor's or Master's Degree in Electrical Engineering along with minimum of 6 years of experience over similar area.
- Excellent written and verbal communications skills.
- Solid hardware design concepts and experience.
- Strong analytical skills for problem abstraction and resolution.
- Good understanding of high-speed IO debug methods preferably PCIe or Ethernet technologies (signal integrity, firmware debug, protocol analysis).
- Working knowledge of lab equipment including oscilloscope, network analyzer, spectrum analyzer, logical analyzer, protocol analyzer, etc.
- Self-motivated with the ability to work independently and deliver quality result.
Preferred Qualifications:
- Knowledge of PCIe building block on SerDes PHY layer, Data Link layer, Transaction Layer. Fluent on PCIe link issue debug including SerDes Equalization and LTSSM log analysis.
- Knowledge of Intel system level architecture BMC, NCSI, I2C, IOSF, I3C.
- Working knowledge of 10G/25G/40G/100G/200G/400G Ethernet media (Optical, DAC, Backplane), and proven experience on resolving Ethernet interlink issue.
- Working knowledge of Ethernet module manageability protocol including, SFF-8472, SFF-8636, CMIS 3.x/4.x/5.x
- Proven experience of supporting custom design and issue debug activities.
- Proven experience of product development, from hardware design to mass production.
- Proven experience of x86 Server platform design.
- Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Job Type:Experienced HireShift:Shift 1 (Taiwan)Primary Location: Taiwan, TaipeiAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Bachelor's or Master's degree in Electrical Engineering
- At least 6 years of experience in a similar area
- Excellent written and verbal communication skills
- Solid hardware design concepts and experience
- Strong analytical skills for problem abstraction and resolution
- Working knowledge of high-speed I/O debugging, preferably PCIe or Ethernet
- Experience with signal integrity, firmware debugging, and protocol analysis
- Working knowledge of oscilloscopes, network analyzers, spectrum analyzers, logic analyzers, and protocol analyzers
- Ability to work independently and deliver quality results
- Knowledge of PCIe SerDes PHY, Data Link, and Transaction layers
- PCIe link debugging experience, including SerDes equalization and LTSSM log analysis
- Knowledge of BMC, NCSI, I2C, IOSF, and I3C
- Experience with 10G, 25G, 40G, 100G, 200G, or 400G Ethernet media
- Experience resolving Ethernet interlink issues
- Knowledge of Ethernet module management protocols including SFF-8472, SFF-8636, and CMIS 3.x/4.x/5.x
- Experience supporting custom design and issue debugging
- Product development experience from hardware design through mass production
- Experience with x86 server platform design
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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