Memory Subsystem Architect (NPU)

About Bitdeer:

Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud.
Bitdeer is committed to providing comprehensive Bitcoin mining solutions for its customers. Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles complex processes involved in computing across the value chain. This includes equipment procurement, transport logistics, datacenter design and construction, equipment management, and network and facility operations. Bitdeer also offers advanced cloud capabilities to customers with a high demand for artificial intelligence.
Headquartered in Singapore, Bitdeer operates globally with a diversified 3 GW energy portfolio, and deploys Bitcoin mining and HPC datacenters in the United States, Bhutan, Norway, Canada, Malaysia, and Ethiopia.

About the role

You will own the architecture of our in-house memory subsystem: the controller and the complete interface to a four-high CHENXING2 3D-DRAM stack bonded onto the logic die. This is the function that turns raw DRAM bandwidth into delivered inference performance, and it sits at the intersection of the NPU dataflow, the NoC, the 3D stack and the thermal envelope. Because we do not license a memory controller, your decisions on scheduling, address mapping, refresh, ECC/RAS and thermal-aware throttling directly define the chip’s real-world throughput. It is a senior, hands-on architecture role with end-to-end ownership from spec through silicon bring-up.

Key responsibilities:

• Controller architecture - define the microarchitecture of the in-house 3D-DRAM memory controller: command scheduling, bank/rank/channel parallelism, request reordering, write/read turnaround and arbitration policy.
• Bandwidth, latency & QoS -  set and defend bandwidth/latency/QoS targets for NPU tile traffic and CPU/IO traffic; design the QoS and priority scheme jointly with the NoC architect to keep the tile array fed.
• Address & bank mapping - design address-to-bank/channel mapping optimized for NPU access patterns (GEMM/attention/conv tiling) and the 4-layer stack topology.
• Refresh, ECC & RAS - architect refresh scheduling, ECC, error logging, repair hooks and the broader RAS strategy in coordination with CreMemory’s BIST/repair flow.
• Thermal-aware scheduling - design throttling and thermal-aware scheduling hooks for DRAM-on-logic operation; co-own the throttling policy with the thermal and power owners. (This is a make-or-break item for the stack.)
• Vendor PHY/model interface - own the DFI-style/vendor interface to the CreMemory 3D-DRAM PHY; specify and review the CreMemory deliverable requirement lists we must provide on time (lib, CPM, LEF, simulation/timing models, corners).
• Performance modeling - build or direct cycle-approximate memory performance models; run trade-off studies that feed the full-chip performance model and architecture freeze.
• Verification & sign-off - define the memory and 3D co-verification plan with the DV team (no purchased VIP), including DFI-interface checks, refresh/ECC/RAS scenarios and thermal-throttle behavior.
• Cross-team & vendor leadership - drive the technical relationship with CreMemory (models, corners, joint debug SLAs) and mentor existing engineers into the memory-controller RTL and DV roles.

Required qualifications:

• 8+ years in memory-subsystem / DRAM-controller architecture or design, with at least one controller shipped to silicon (DDR/LPDDR/HBM or a custom 3D-DRAM/stacked-memory controller).
• Deep command of DRAM operation and controller microarchitecture: command scheduling, bank management, refresh, timing parameters, write/read turnaround and bandwidth-efficiency trade-offs.
• Hands-on experience with a DFI-style or custom PHY/controller interface and with integrating vendor-delivered PHY IP and timing models.
• Working knowledge of ECC, error reporting, repair and RAS strategy for memory.
• Ability to build or direct bandwidth/latency performance models (C++/SystemC/Python) and to translate workload traffic into architecture decisions.
• Strong written specs and the ability to drive cross-functional and vendor technical reviews.
  

Preferred / differentiators:

• Experience with 3D-stacked memory, HBM, hybrid bonding or Wafer-on-Wafer integration.
• Exposure to AI-accelerator or GPU memory traffic and NPU/dataflow co-design.
• Familiarity with thermal-aware throttling and power/performance management for stacked dies.
• Experience defining a verification plan without purchased VIP (in-house checkers, assertions, scoreboards).
• Prior work with a DRAM vendor as an IP/model consumer (deliverable definition, corner coverage, joint debug).

What success looks like (first 6–12 months): 

• Memory subsystem spec frozen and aligned with the NPU, NoC and 3D/thermal architectures.
• CreMemory deliverable requirement lists (lib/CPM/LEF/models) issued on schedule so vendor delivery is not gated by us.
• A credible bandwidth/QoS model that the full-chip performance model can build on.
• A memory + 3D co-verification plan agreed with DV, and the controller RTL effort staffed and mentored.

What you will experience working with us:

• A culture that values authenticity and diversity of thoughts and backgrounds;
• An inclusive and respectable environment with open workspaces and exciting start-up spirit;
• Fast-growing company with the chance to network with industrial pioneers and enthusiasts;
• Ability to contribute directly and make an impact on the future of the digital asset industry;
• Involvement in new projects, developing processes/systems;
• Personal accountability, autonomy, fast growth, and learning opportunities;
• Attractive welfare benefits and developmental opportunities such as training and mentoring.

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Bitdeer is committed to providing equal employment opportunities in accordance with country, state, and local laws. Bitdeer does not discriminate against employees or applicants based on conditions such as race, colour, gender identity and/or expression, sexual orientation, marital and/or parental status, religion, political opinion, nationality, ethnic background or social origin, social status, disability, age, indigenous status, and union.