Memory Layout Design Engineer

Posted 3 Days Ago
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Hiring Remotely in Electronics City, Bangalore, Karnataka, IND
Remote
Mid level
Software • Semiconductor • Manufacturing
The Role
Designs and verifies memory layouts for advanced CMOS semiconductor processes. Responsibilities include applying process rules, floor-planning, hierarchy layout, chip integration, signal and power planning, physical verification, scheduling, and delivering quality layouts. The role also supports methodology development, technology reviews, junior engineer training, and collaboration with SOC and library teams. Experience with memory architecture, memory compilers, automation, scripting, and SKILL programming is beneficial.
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Job Description:

Job Requirements:
  - Minimum 3 years of experience with strong layout knowledge.
  - Bachelor's degree required.
  - Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - CALIBRE & Hercules).
  - Strong layout knowledge in submicron processes (e.g., A14, 2nm, 3nm, 5nm, 7nm).
  - Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.
Job Description:
  - Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout.
  - Manage scheduling, timelines, and layout floor-planning.
  - Responsible for start-to-end deliverables with quality within the planned schedule.
  - Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team.
Skill Set (Memory):
  - Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.
  - Experience with Cadence Layout tools (VIRTUOSO XL, VXL, or EXL) and CALIBRE verification tools.
  - Proficiency in floor-planning, hierarchy layout, and chip integration.
  - Understanding of memory architecture, RC requirements, and the ability to plan signal and power based on layout guidelines.
  - Knowledge of AI, automation in layout, Script Programming, and SKILL Programming is a plus.
  - Ability to lead, train junior engineers, and manage projects effectively.
  - Good knowledge of memory layout topology; experience with memory compilers is a plus.
  - Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.
  - Self-reliant with the ability to work both independently and collaboratively.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Skills Required

  • Minimum 3 years of experience with strong layout knowledge
  • Bachelor's degree
  • Proficiency with Cadence Virtuoso Layout, Layout XL, Schematic Capture, CALIBRE, and Hercules verification tools
  • Strong layout knowledge in submicron processes, including A14, 2nm, 3nm, 5nm, or 7nm
  • Experience in digital layout, including standard cell, memory, and I/O layout
  • Strong experience in memory layout design and physical verification in CMOS processes
  • Experience with Cadence Virtuoso XL, VXL, or EXL and CALIBRE verification tools
  • Proficiency in floor-planning, hierarchy layout, and chip integration
  • Understanding of memory architecture and RC requirements
  • Ability to plan signal and power according to layout guidelines
  • Ability to lead, train junior engineers, and manage projects
  • Ability to lead technology reviews and document layout methodologies, flows, and guidelines
  • Analog layout experience
  • Knowledge of AI and layout automation
  • Script programming and SKILL programming
  • Experience with memory compilers

Broadcom Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Broadcom and has not been reviewed or approved by Broadcom.

  • Equity Value & Accessibility — Equity grants, including RSUs, stock refreshers, and an ESPP, are often described as top-tier and a primary driver of strong total compensation, especially for technical and senior roles. Once stock begins vesting, overall pay is commonly viewed as hard for other employers to match.
  • Retirement Support — A 401(k) match of 100% up to 6% with immediate vesting is frequently highlighted as a standout benefit. This structure provides strong long-term savings support.

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The Company
HQ: Palo Alto, CA
38,985 Employees
Year Founded: 1991

What We Do

Broadcom Inc. (NASDAQ: AVGO) is a global technology leader that designs, develops and supplies semiconductor and infrastructure software solutions.

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