Logic Design Methodology Engineer

Job Details:

Job Description: 

Come join us as a Logic Design Methodology Engineer and together let's grow and develop the next leading technology.

As the Logic Design Methodology Engineer of the Platform Engineering Solution Group (PESG) - Frontend CAD customer enablement and methodology team, you will be responsible for driving definition and enablement of tools, flows and methodologies (TFMs) of the frontend CAD team to internal customers and ensuring their success in productively using the Frontend CAD TFMs. You will collaborate with design automation technical leads, design domain leads, and domain managers to orchestrate activities that drive new methodologies from concept to full production, which are to be adopted in new projects. If you find it exciting to work in a diverse team that innovates with other Intel advanced technology groups, with other industry leaders, and in academia, then we have your opportunity. In this position, we are looking for a phenomenal engineer to join our world-class enablement and methodology team to expand the technology that provides Intel with advantages in Frontend design.
Job Responsibilities:

• Lead customer-facing initiatives across Frontend (FE) domains such as RTL and Design Verification (DV), engaging directly with customers to organize and execute strategies from proof of concept to successful deployment of frontend CAD tools, flows and methodologies.
• Gather and implement customer feedback, manage TFM documentation, conduct system-level testing, drive methodology improvements, and support customers to ensure productive use of TFMs.
• Oversee a multi-site initiative, collaborating with key customers, including server, clients and IP design teams across the United States, to enable the deployment, validation, and release of high-quality design systems.
• Maintain constant communication with customers, proactively identify potential issues, and drive appropriate solutions.
• Serve as a liaison between customers, development teams, and vendors, integrating state-of-the-art design solutions (EDA tools, flows, and methodologies) sourced externally or developed internally to build sustainable and scalable solutions for multiple chip design projects.
• Collaborate with design automation technical leads, design domain leads, domain managers, and EDA Vendors to orchestrate the development of new design automation methodologies and tool capabilities from concept to full production, enhancing design quality, reducing cycle time, and optimizing designs for new projects.
• Partner with design system development engineering and design infrastructure engineering teams to enable the deployment validation and release of high-quality design systems.

The ideal candidate should exhibit the following behavioral traits:

• Working with a large and globally spread teams and building consensus.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• Minimum Qualifications:

The candidate must have a Bachelor's Degree in Electrical/Computer Engineering, Computer Science, or related major with 10+ years' experience -OR- a Master's Degree in Electrical/Computer Engineering, Computer Science, or related major with 8+ years' experience with:

• Deploying, supporting, or developing and managing frontend CAD tools such as simulation, emulation, static checks, connectivity, handoff to backend etc.
• Managing development, development or supporting Frontend CAD tools and flows
• System Verilog HDL compilers parsers simulators linters profiling and debugging tools.
• Programming in scripting languages Perl or TCL
• Direct hands-on experience in one or more of the following areas: EDA/CAD vendor tools (Cadence: Xcelium, Palladium, vManager, Indago etc. , Synopsys:VCS, Zebu, Spyglass, VC Spyglass, VMS, Verdi etc.) experience
• Preferred Qualifications:

Background of EDA tools, flow and methodology.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, California, Santa Clara

Additional Locations:US, California, Folsom, US, Massachusetts, Hudson, US, Oregon, Hillsboro, US, Texas, Austin

Business group:The Client Engineering group (CEG) is a worldwide organization focused on the development and integration of SOCs, and critical IPs that power Intel's leadership products, driving the Client roadmap for CCG, and invest in future disruptive technologies.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$186,070.00-$262,680.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.