Understand/review Design specification and develop verification strategy/Test plan/coverage plan. Development of constrained random verification environments and verification components. Writing tests/sequences/functional coverage/assertions to meet verification goals. Developing c-based test cases for SOC verification.
Required experience
- Strong background on functional verification fundamentals, environment planning, test plan generation, environment development
- System Verilog experience and experience with UVM based functional verification environment development is required.
- Good knowledge of verilog/vhdl/C/C++/Perl/Python.
- Expertise in AMBA protocols. (AXI/AHB/APB).
- Good knowledge of at least one of the USB/PCIE/Ethernet/DDR/LPDDR or similar protocols
- Good handle on using one or more version control software
- Good handle on using one or more load sharing software
Desirable skills and experience
- Prior experience with Cadence tools and flows is highly desirable.
- Familiarity with ARM/CPU architectures is a plus.
- Experience in developing c-based test cases for SOC verification
- Some experience with assembly language programming
- Good knowledge of some of the protocols like UART, I2C, SPI, JTAG
- Embedded C code development and debug
- Formal Verification experience
Strong vocabulary, communication, organizational, planning, and presentation skills are essential. Ability to work independently and productively with high quality output and results in a fast paced and dynamic environment. Ability and desire to learn new methodologies, languages, protocols etc. Must be open to constant personal development and growth to meet the evolving demands of the semiconductor industry. Self-motivated and willing take up additional responsibilities to contribute to team’s success.
We’re doing work that matters. Help us solve what others can’t.Skills Required
- Strong background on functional verification fundamentals
- System Verilog experience
- Experience with UVM based functional verification
- Good knowledge of Verilog/VHDL/C/C++/Perl/Python
- Expertise in AMBA protocols (AXI/AHB/APB)
- Good knowledge of USB/PCIe/Ethernet/DDR/LPDDR protocols
- Experience with version control software
- Experience with load sharing software
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
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