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Job Description: This position is in Cadence Pegasus Physical Verification R&D team in Hsinchu, Taiwan. The candidate for this position will be developing design rule check (DRC) and FILL decks for advanced nodes of semiconductor manufacturing, The job involves creating quality check (QC) patterns, writing physical verification DRC and FILL rules and developing decks consisting of these rules. It also involves testing these decks on real customer designs and troubleshooting the deck and tool issues, providing feedback to Pegasus Foundry Team, Pegasus R&D, and foundry partners.
Requirement: At least 2 years of previous experience with DRC or FILL deck development, and BS or MS degree in engineering.
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Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
