Lead Software Engineer

Posted 4 Days Ago
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Noida, Gautam Buddha Nagar, Uttar Pradesh, IND
In-Office
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Lead the design, development, validation, and delivery of formal verification IPs for industry-standard protocols. Responsibilities include creating RTL models and SystemVerilog Assertions, developing verification plans, applying formal methodologies, debugging with EDA tools, building Python and Tcl automation, managing regressions and coverage closure, mentoring engineers, and collaborating with application engineering and customer teams.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial and healthcare.


The Cadence Advantage

  • The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
  • Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
  • The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
  • Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
  • You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

 

Job Summary

In this role, you will independently own the design, development, validation, and delivery of Formal Verification IPs, including Verilog design models and SystemVerilog Assertions for industry-standard protocols.



Job Responsibilities:

  • This role involves the design, development, and delivery of Assertion-Based Verification IPs for industry-standard protocols, with ownership of technical execution and quality.
  • Analyze protocol specifications and translate requirements into robust formal verification plans, design models, SystemVerilog Assertions, assumptions, and coverage.
  • Own the end-to-end development and maintenance of Assertion-Based Verification IPs, including architecture, implementation, validation, regression, release readiness, and documentation.
  • Develop synthesizable RTL and verification components using strong RTL design, synthesis, and SystemVerilog concepts.
  • Apply formal verification methodologies to prove complex protocol and design properties, identify convergence challenges, and implement effective abstractions and constraints.
  • Create verification plans, define measurable coverage goals, review results, and drive closure of functional and formal coverage gaps.
  • Debug complex design and verification failures using EDA tools, perform root-cause analysis, and deliver high-quality, scalable solutions.
  • Build and enhance automation, regression, and productivity flows using scripting languages such as Python and Tcl.
  • Provide technical guidance through design and code reviews, mentor junior engineers, and contribute to verification methodology and process improvements.
  • Collaborate with Application Engineering teams and geographically distributed teams to resolve technical issues and meet delivery commitments.
  • Communicate technical risks, dependencies, progress, and recommendations clearly to stakeholders, and support customer-facing technical discussions when required.
  • undefined 

  • Qualifications BE/BTech/ME/MS/MTech in Electrical/Electronics 

  • Experience and Technical Skills Required

  • 5+ years of experience in RTL design/Verification in case of BE/BTECH or Masters Degree with 3+ years of experience.

  • Verilog/SystemVerilog and SVARTL design or verificationFormal verification concepts and tools would be plus point.

  • Verification planning and coveragePython/Tcl scriptingAt least one protocol such as AXI, CHI, PCIe, or CXLWorking knowledge of AI/ML concepts and experience using AI-assisted tools to improve verification, debugging, automation, or engineering productivity.  

  • Behavioral skills requiredMust possess strong written, verbal and presentation skills.Ability to establish a close working relationship with both customer peers and management.Explore what’s possible to get the job done, including creative use of unconventional solutions.Demonstrate strong ownership, sound technical judgment, and the ability to drive complex assignments independently from planning through delivery.undefined
We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • BE/BTech/ME/MS/MTech degree in Electrical or Electronics Engineering
  • 5+ years of RTL design or verification experience with a BE/BTech, or 3+ years with a master's degree
  • Experience with Verilog and SystemVerilog
  • RTL design or verification experience
  • Verification planning and coverage experience
  • Python and Tcl scripting experience
  • Experience with at least one protocol such as AXI, CHI, PCIe, or CXL
  • Working knowledge of AI/ML concepts and experience using AI-assisted engineering tools
  • Strong written, verbal, and presentation skills
  • Ability to work independently and establish relationships with customers, peers, and management

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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