Lead Software Engineer

Posted 9 Hours Ago
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San Jose, CA, USA
In-Office
115K-213K Annually
Entry level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Develop and optimize Cadence Innovus place-and-route software focused on chip timing, power consumption, and timing closure. Design multithreaded and distributed optimization solutions using strong software engineering, data structures, and algorithmic skills. Collaborate with customers and contribute to physical synthesis, timing analysis, and IC physical design tools. Work primarily in C/C++ on Linux, with Tcl and scripting experience preferred.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This R&D engineer role is part of the timing optimization group of Cadence’s Innovus Place & Route product.   This key Innovus R&D group is responsible for optimizing timing (how fast a chip functions) and power (the power consumption of the chip), and the timing closure flow.  The Innovus product is a key product used by a variety of chip manufacturing companies such as mobile, automotive, CPU & GPU cores, & AI.  The work done in this high-performance team has a huge impact on the chip industry and products that are used in our daily lives.

We are looking for talented candidates with a strong background in electronic design automation (timing, power analysis, optimization), and excellent software engineering skills, experience with multithreaded and distributed optimization.  We are looking for individuals that can make the next breakthrough in the technology that we provide to the customers, making a big impact to the industry.

Minimum Qualifications:
Highly technical engineer with excellent problem solving skills
C/C++ software development experience in Linux environment
Strong understanding and extensive usage of data structures and algorithms
Great communication skills and a strong desire for working with customers
MS (Ph.D. track a plus) in Electrical Engineering, Computer Science.
Preferred:
Knowledge of physical synthesis algorithms, timing analysis and multithreading is a strong plus.
Prior R&D experience working on IC physical designs tools
Hands on experience using the above physical design tools for design closure and knowledge of physical design flows a plus.
Experience with Tcl and other scripting languages

The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • Excellent problem-solving skills
  • C/C++ software development experience
  • Experience developing in a Linux environment
  • Strong understanding and extensive use of data structures and algorithms
  • Strong communication skills and willingness to work with customers
  • MS degree in Electrical Engineering or Computer Science
  • PhD-track education
  • Knowledge of physical synthesis algorithms
  • Knowledge of timing analysis
  • Multithreading experience
  • Prior R&D experience with IC physical design tools
  • Hands-on experience using physical design tools for design closure
  • Knowledge of physical design flows
  • Experience with Tcl and other scripting languages

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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