Lead Software Engineer - Logic Synthesis

Reposted Yesterday
Be an Early Applicant
Shanghai, Shanghai Municipality, Shanghai, CHN
In-Office
Mid level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Develop and maintain the Palladium logic synthesizer, add VHDL/Verilog feature support, optimize logic and performance, and collaborate across sites. Support design modeling and verification workflows.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description:

  • Responsible for development and maintenance of the synthesizer for Palladium.
  • Implementation for new VHDL/Verilog feature support in synthesizer.
  • Logic optimization and performance improvement in synthesizer.

Position Requirement:

  • This position requires a Bachelor or Master's degree in EE/CS/CE with 3-5 years of industry experience.
  • Candidate should be proficient with C/C++, Operating system concepts.
  • Design modeling using Verilog/SV, VHDL or SysC.
  • Knowledge and experience in RTL modeling of BFMs along with exposure to verification methodologies using UVM and SC/TLM is preferable.
  • EDA/CAD tool development experience or logic design verification experience is highly preferred.
  • Knowledge and experience in AI tools like Copilot or Claude code is preferred.
  • Requires good communication skills, attention to details, and ability to work in multi-site/multi-person project.
We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • Bachelor's or Master's degree in EE, CS, or CE with 3-5 years industry experience
  • Proficiency with C/C++
  • Knowledge of operating system concepts
  • Design modeling using Verilog, SystemVerilog, VHDL, or SystemC
  • Good communication skills, attention to detail, ability to work in multi-site/multi-person projects
  • RTL modeling of BFMs and exposure to verification methodologies using UVM and SC/TLM
  • EDA/CAD tool development or logic design verification experience
  • Experience with AI coding tools (e.g., Copilot, Claude)

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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