Lead Product Engineer

Posted 5 Days Ago
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Bangalore, Bengaluru Urban, Karnataka, IND
In-Office
Entry level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Perform product engineering for Cadence Genus logic synthesis software, optimizing power, performance, and area for digital ASICs. Validate new features, solve physical-aware synthesis challenges, support field engineers and customers, verify interoperability with Cadence tools, and document product requirements. The role requires debugging complex logic, physical design, timing closure, and synthesis problems while communicating solutions to customers and R&D.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job responsibilities:

  • Perform Product Engineering work for Genus Synthesis Solution (Genus), a logic synthesis software used for synthesizing a design described in a high-level language into logic gates, to achieve best-in-class Power, Performance & Area (PPA) for latest digital ASICs

  • Understand the internal flow within the Genus for newly developed features and verify the correctness and perform experiments to determine an optimal solution

  • Solve new and challenging problems in physical aware synthesis space with the goal to bridge the gap between logic synthesis and place and route

  • Support the field engineers in Cadence Design Systems, Inc. and its customers in using Genus. In addition, interface between R&D and customer as the first line of support for the R&D and the customers

  • Provide support to verify the interoperability of Genus with other digital logic software tools within Cadence Design Systems, Inc. to provide seamless flows

  • Understand the future requirements of the software by interfacing with the internal and external customers of Genus and document the Product Requirement Specifications (PRS) for newly developed features using the standard documentation software

Preferred Qualifications:

  • Experience in design and EDA with an emphasis on Cadence tools of Synthesis, Physical Design & timing closure at 20nm or below nodes

  • Prior Designer, Product Engineering or Application Engineering experience in digital implementation, especially synthesis

  • Understand industry challenges in digital implementation & sign off domain with exposure to 28nm & below foundry process nodes

  • Industry experience with EDA tools in the IC digital implementation flow, preferably on Genus and Innovus

  • Experience in Logic Design and Synthesis, Formal Verification, Low Power design, Physical Design and Timing Closure for block level and top level designs

  • Automation skills using Perl, Tcl and shell scripting essential

  • Knowledge of HDL – Verilog or System Verilog is preferred

  • Must have logic design and timing closure skills

  • Strong analysis skills required to debug complex timing closure, logical and physical design problems. Ability to perform root-cause analysis to suggest solutions to customers and provide feedback to R&D

Qualifications

  • BE/BTech/ME/MS/MTech or equivalent

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • BE, BTech, ME, MS, MTech, or equivalent degree
  • Automation skills using Perl, Tcl, and shell scripting
  • Logic design and timing closure skills
  • Strong analysis skills for debugging complex timing closure, logical design, and physical design problems
  • Experience in design and EDA, including Cadence synthesis, physical design, and timing closure tools at 20nm or below nodes
  • Prior designer, product engineering, or application engineering experience in digital implementation, especially synthesis
  • Experience with digital implementation and sign-off challenges involving 28nm and below foundry process nodes
  • Industry experience with EDA tools in IC digital implementation flows, preferably Genus and Innovus
  • Experience in logic design and synthesis, formal verification, low-power design, physical design, and timing closure
  • Knowledge of Verilog or SystemVerilog

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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