Lead Physical Design Engineer

Posted 7 Hours Ago
Be an Early Applicant
Nanjing, Jiangsu, CHN
In-Office
Mid level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Leads block- and chip-level physical design, including floorplanning, placement, clock-tree synthesis, routing, physical verification, static timing analysis, and EM/IR analysis. Resolves DRC, DFM, LVS, antenna, and ERC violations for advanced process nodes. Requires strong process design-rule knowledge, physical implementation experience, communication skills, independent thinking, and teamwork.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Physical Implementation Engineer

Job Description:

- A role of block/chip level physical design engineer;

- Job content includes:

- Physical Design, including: floorplan, placement, CTS, routing, etc. ;

- Physical Verification;

- Static Timing Analysis;

- EM/IR Analysis.

Job Qualification:

- Rich knowledge of the design rule for the process of N28/N16 and below;

- Ability of fixing the physical design violations, including: DRC, DFM, LVS, ANT, ERC etc.;

- Experience in chip level physical verification is preferred;

- Basic knowledge/experience of the physical implementation and static timing analysis;

- Bachelor or above degree in majors of EE/CS/IT, with more than 3 years’ work experience;

- Good ability of effective learning and independent thinking;

- Good ability of communication and teamwork;

- Carefulness, responsibility and persistence.

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • Bachelor's degree or higher in Electrical Engineering, Computer Science, Information Technology, or a related major
  • More than 3 years of work experience
  • Strong knowledge of design rules for N28, N16, and smaller process nodes
  • Ability to fix physical design violations including DRC, DFM, LVS, ANT, and ERC
  • Basic knowledge or experience in physical implementation and static timing analysis
  • Chip-level physical verification experience
  • Effective learning and independent thinking abilities
  • Strong communication and teamwork abilities
  • Carefulness, responsibility, and persistence

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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