Lead Physcial Design Engineer

𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀

𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟭𝟮𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟰𝟱𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟭𝟮-𝟰𝟱 𝗟𝗣𝗔)

Experience: 4+ yrs

Location: Bengaluru

Job Type: Full-time

We are looking for an experienced Lead Physical Design Engineer to drive the implementation of high-performance semiconductor designs from RTL handoff through GDSII while ensuring optimal power, performance, and area (PPA). This role is ideal for professionals with deep expertise in Physical Design, Floor Planning, and Cadence design tools who are passionate about delivering complex SoC and ASIC implementations for advanced technology nodes.

As a Lead Physical Design Engineer, you will collaborate closely with RTL, DFT, STA, Design Verification, and Foundry teams to develop robust physical implementation strategies, optimize chip layouts, and resolve complex design challenges. You will take ownership of the complete physical design flow, mentor engineering teams, and contribute to design methodologies that improve quality, turnaround time, and silicon success. This role offers the opportunity to work on cutting-edge semiconductor products while influencing technical direction and implementation best practices.

• Lead end-to-end physical design implementation from netlist through GDSII for complex ASIC and SoC designs.
• Develop and optimize floor planning strategies to achieve power, performance, area (PPA), and manufacturability targets.
• Perform placement, clock tree synthesis (CTS), routing, timing closure, and physical verification using Cadenceimplementation tools.
• Collaborate with RTL, DFT, STA, and verification teams to resolve design issues and ensure successful physical implementation.
• Drive timing closure by optimizing setup, hold, signal integrity, congestion, IR drop, electromigration, and power distribution challenges.
• Conduct physical design reviews, identify implementation risks, and recommend design improvements to enhance overall chip quality.
• Support ECO implementation, design optimization, and signoff activities while ensuring adherence to project schedules.
• Work closely with foundry and packaging teams to address manufacturability, reliability, and tape-out requirements.
• Mentor junior engineers, establish physical design best practices, and contribute to methodology improvements and automation initiatives.
• Prepare technical documentation, implementation reports, and project status updates while collaborating with cross-functional stakeholders.

• 4+ years of hands-on experience in Physical Design for ASIC or SoC development.
• Strong expertise in Floor Planning, placement, CTS, routing, timing closure, and physical signoff methodologies.
• Extensive experience with Cadence physical design tools, including Innovus and related implementation solutions.
• Solid understanding of advanced technology nodes, low-power design techniques, clock distribution, congestion analysis, and PPA optimization.
• Experience with STA, IR drop analysis, signal integrity, electromigration, DRC/LVS, and physical verification flows.
• Familiarity with TCL, Perl, Python, or shell scripting for automation and design flow optimization.
• Strong understanding of semiconductor design methodologies, foundry requirements, and tape-out processes.
• Excellent analytical, debugging, and problem-solving skills with the ability to resolve complex implementation challenges.
• Proven ability to lead technical initiatives, mentor engineering teams, and collaborate effectively across cross-functional design organizations.
• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related discipline, with a passion for delivering high-quality semiconductor products.