Lead Functional Product Engineer, Power Analysis

Posted 2 Days Ago
Be an Early Applicant
San Jose, CA, USA
In-Office
115K-213K Annually
Mid level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Develop, debug, and deploy signoff power analysis flows at customer sites. Reproduce and resolve customer issues, validate tools, optimize power results, automate deployments, and document best practices and findings.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are looking for a skilled engineer to join our Power Analysis team, focused on developing, debugging, and deploying Signoff power analysis flows at customer environments.

Key Responsibilities
  • Closely work with R&D to develop and maintain Signoff power analysis flows including integration with synthesis and PnR stages 
  • Reproduce, debug, and resolve customer-reported issues in power analysis tools and flows
  • Deploy and validate power analysis tools at customer sites; provide hands-on technical support
  • Collaborate with customers to optimize power results and improve flow efficiency
  • Contribute to flow automation and scripting for repeatable deployments
  • Document debug findings, best practices, and flow guidelines
Required Skills
  • Hands-on experience with Signoff power analysis (static and dynamic power)
  • Knowledge of power optimization techniques in Synthesis (clock gating, operand isolation, multi-Vt cell selection, 
  • Working knowledge of UPF (Unified Power Format) — power domains, isolation, level shifting, retention
  • Proficiency in Verilog/SystemVerilog for design analysis and testcase creation
  • Understanding of digital design fundamentals — clock domains, pipeline stages, timing/power trade-offs
  • Experience with low-power design methodologies (DVFS, power gating, multi-voltage)
  • Familiarity with Liberty (.lib) and SPEF formats
  • Scripting skills: Tcl, Python, or Shell
  • Familiarity with tools such as Joules, Voltus, PTPX or equivalent
Education & Experience
  • B.E./B.Tech or M.E./M.Tech in Electronics / VLSI / Computer Engineering or equivalent 
  • Must have 3+ years of industry work experience

The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • Hands-on experience with Signoff power analysis (static and dynamic power)
  • Knowledge of power optimization techniques in synthesis (clock gating, operand isolation, multi-Vt cell selection)
  • Working knowledge of UPF (Unified Power Format) including power domains, isolation, level shifting, retention
  • Proficiency in Verilog/SystemVerilog for design analysis and testcase creation
  • Understanding of digital design fundamentals (clock domains, pipeline stages, timing/power trade-offs)
  • Experience with low-power design methodologies (DVFS, power gating, multi-voltage)
  • Familiarity with Liberty (.lib) and SPEF formats
  • Scripting skills: Tcl, Python, or Shell
  • Familiarity with tools such as Joules, Voltus, PTPX or equivalent
  • B.E./B.Tech or M.E./M.Tech in Electronics / VLSI / Computer Engineering or equivalent
  • Minimum 3+ years of industry work experience

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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