JOB Description:
**RESPONSIBILITIES:**
- Development of test plans, tests, and verification infrastructure for complex IP’s/sub-systems/SOC’s.
- Creation of verification environment using UVM methodology or equivalent.
- Construction of reusable bus functional models, monitors, checkers, and scoreboards.
- Leading functional coverage verification closure.
**SKILL SETS:**
- BTech/ MTech in Engineering. Or Equivalent or Relavent
- 4-7 years of VLSI industry experience in Verification. Equivalent or Relavent
- Expertise in SoC level verification and IP/Subsystem validation.
- Proficiency in developing test bench/testbench components, test plans, test cases, functional coverage, assertions, and coverage analysis.
- Strong knowledge of UVM, SV.
- Familiarity with protocols like UCIe, PCIe, DDR, USB, AMBA.
- Skilled individual contributor and mentor with exceptional debug and problem-solving abilities.
- Extensive experience in the verification cycle for complex SOCs.
Skills Required
- BTech or MTech in Engineering or equivalent
- 4-7 years of VLSI industry experience in Verification
- Expertise in SoC level verification and IP/Subsystem validation
- Proficiency in developing test bench components and functional coverage
- Strong knowledge of UVM and SystemVerilog
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
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