Lead Design Engineer

Reposted 14 Days Ago
Be an Early Applicant
Hyderabad, Telangana, IND
In-Office
Mid level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Responsible for developing and integrating foundry rule decks, QA of PDKs, and automating verification processes using various programming languages.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description:     

  • To develop & integrate foundry rule decks & technology files to support PDKs by using foundry provided process design kits as a starting point.
  • PDK QA, verification and release methodology for decks and specialized setups including track patterns to aid in layout.
  • Responsible for physical verification methodology, including installation, development, qualification, automation, and support –
    • To develop scripts to automate LVS, DRC, RM,IR and Parasitic Extraction flows.
    • And to support layout teams in verification flow issues.
  • Ensuring QA of the integrated PDK’s with the custom design environment
    • Add sub scripts to improve efficiency on QA process with adequate coverage.
  • General tool usage support – real-time support of all tools, creating bug workarounds and filing CCRs with R&D
  • Responsible for rule deck development - to implement process design rules into physical verification rules decks and QC for the rule decks.
  • Responsible for interfacing with the design teams and foundry team to develop and verify our PDKs.
  • Develop, own and maintain an automation frame work for efficiency improvement perspective for the design environment.

                                                              

Position Requirements:

  • Bachelor’s Degree in Electrical/Electronic Engineering or equivalent .
  • 4-7 years of Work experience in PDK development and CAD enablement.
  • Expertise in Cadence Python, SKILL, Perl programming languages.
  • Knowledge of deep sub-micron CMOS processes, device physics and layout design.
  • Experience with Cadence custom IC Virtuoso platform to create layout test structures, to validate verification rules and to troubleshoot errors.
  • Experience in developing PDK device library components and definitions including SKILL parameterized cells (Pcell), symbols, CDF, callbacks, simulation/netlisting.
  • Experience with physical verification tools for DRC, LVS and parasitic extraction, Cadence PVS, Assura is a plus.
  • Working knowledge of revision control software (Git, sos, Subversion, Synchronicity, etc)
  • Understanding on Pcell creation and enhancements to pcell parameters, device call backs etc is a plus
  • Excellent technical problem solving skills.
  • Excellent communication and presentation skills.
We’re doing work that matters. Help us solve what others can’t.

Top Skills

Assura
Cadence
Cadence Virtuoso
Git
Perl
Python
Skill
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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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