We are looking for a Lead Design Engineer to provide hands-on execution across Synthesis, LEC, CLP, and UPF/power-intent flows for advanced ASIC/SoC designs. This role is execution-focused with growing ownership: debugging synthesis and LEC issues independently, contributing to CLP sign-off, and writing constraints and ECO scripts, while working closely with the Team on complex escalations.
Key Responsibilities- Run and debug LEC sign off on design blocks; investigate and resolve NEQs and constraint mismatches
- Work on Genus synthesis runs to improve QoR, debug SDC/constraint issues.
- Support CLP flows
- Write and maintain ECO scripts and timing/power constraints for design blocks
- Independently triage and document issues, escalating complex or systemic issues as needed.
- Collaborate with PD, DFT, and RTL teams to resolve cross-functional issues affecting synthesis/LEC/CLP closure
- Prepare clear status updates and technical summaries for internal tracking
- 4–7 years of hands-on experience in ASIC synthesis, LEC, and/or low-power verification flows
- Working knowledge of Cadence Genus and Conformal (LEC and/or CLP)
- Familiarity with UPF/CPF-based power intent (IEEE 1801)
- Scripting proficiency in Tcl, Perl, or Python; comfortable in Unix/Linux based environments.
- Solid understanding of digital design fundamentals, STA basics, and low-power architecture concepts
- Strong communication skills and ability to work independently on assigned blocks
Skills Required
- 4–7 years of hands-on experience in ASIC synthesis, LEC, and/or low-power verification flows
- Working knowledge of Cadence Genus and Conformal
- Familiarity with UPF/CPF-based power intent and IEEE 1801
- Scripting proficiency in Tcl, Perl, or Python
- Comfort working in Unix/Linux environments
- Solid understanding of digital design fundamentals
- Understanding of static timing analysis basics
- Understanding of low-power architecture concepts
- Strong communication skills
- Ability to work independently on assigned blocks
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
