lead Design Engineer

Posted 11 Days Ago
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Bangalore, Bengaluru Urban, Karnataka, IND
In-Office
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Lead verification of UCIe Controller IP for chiplet and die-to-die interconnect solutions. Develop reusable SystemVerilog/UVM environments, create protocol verification scenarios, execute constrained-random testing, drive functional and code coverage closure, debug regressions, and support verification sign-off. Collaborate with design, architecture, and validation teams to deliver high-quality IP releases.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Job Description: Lead Design Engineer – UCIe Verification

Location: Bangalore, India
Function: Design Verification
Role: Lead Design Engineer – UCIe Controller Verification

Role Overview

We are looking for a highly motivated and technically strong Lead Design Engineer – Verification to join our UCIe verification team in Bangalore.

The candidate will contribute to the verification of complex UCIe Controller IP, working on next-generation chiplet and die-to-die interconnect solutions. The role requires strong hands-on expertise in SystemVerilog/UVM, verification architecture, coverage-driven verification, protocol verification, and debug.

The engineer will work closely with design, architecture, validation, and other cross-functional teams to develop scalable verification environments, validate complex protocol scenarios, drive coverage closure, debug failures, and contribute toward high-quality IP releases.


Required Qualifications
  • BE/BTech/ME/MTech/MS in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.
  • 5+ years of relevant Design Verification experience, with strong hands-on ownership of IP or subsystem-level verification.
  • Strong expertise in: SystemVerilogUVMConstrained-random verificationFunctional coverageCode coverageAssertions/SVARegression and failure debug
  • Experience developing reusable UVM testbench components and verification infrastructure.
  • Strong understanding of verification methodology, test planning, coverage closure, and sign-off.
  • Experience with industry-standard simulators/debug environments such as Cadence Xcelium or equivalent.
  • Ability to analyze complex specifications and translate requirements into effective verification scenarios.
  • Strong debugging and problem-solving skills.
We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • BE, BTech, ME, MTech, or MS in Electronics, Electrical Engineering, Computer Engineering, or a related discipline
  • 5+ years of relevant Design Verification experience
  • Hands-on ownership of IP or subsystem-level verification
  • Strong expertise in SystemVerilog and UVM
  • Experience with constrained-random verification, functional coverage, code coverage, assertions/SVA, regression, and failure debugging
  • Experience developing reusable UVM testbench components and verification infrastructure
  • Strong understanding of verification methodology, test planning, coverage closure, and sign-off
  • Experience with Cadence Xcelium or equivalent industry-standard simulators and debug environments
  • Ability to analyze complex specifications and translate requirements into verification scenarios
  • Strong debugging and problem-solving skills

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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