Lead Design Engineer ( Layout Design )

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success.
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Job responsibilities:

Job Description: Analog Layout Design

Work Location: Hyderabad

Work Experience : 5 – 7 years or equivalent relevant experience.

CV to send K Madhu Prasad [email protected]

Responsibilities:

• Custom layout design for NextGen, high-speed IPs like SerDes/DDR/GDDR/LPDDR/ Pcie/D2D/HBM/Ucie/Chiplets and much more which are yet on the horizon…
• Understanding requirements from different teams and stakeholders be it circuit-design, digital, packaging or foundry and work with a co-creation mindset to successfully deliver Analog Macros *(depending upon level of exp).
• Perform physical verifications
  • Full Spectrum Verifications as per foundry requirements.
  • Flavors of DRC
  • Various Electrical check / LVS /EMIR and Reliability Compliance. 
• Based on expertise level, would be required to not just contribute as an individual contributor, but wear a hat of a leader to lead a team of engineers towards a successful IP delivery. 
• To be agile enough and adapt-with-ease with changing market, client, technology and foundry needs. 

Requirements

•                 Hands-on experience in analog/mixed-signal layout design.

•                 It’s expected to have ownership and hands on high-speed products, classical analog products.

•                 Hands on layout experience in various analog IP like High-speed Analog (Serdes), Data converters, power management and PLL etc.

•                 Having worked on latest technology nodes like 18a, 2nm, 3nm, 5nm, 7nm and below, is desired.

•                 Knowledge of various analog layout techniques, floorplan constraints and IP integration at chip level scenario.

•                 Hands on layout experience in various analog modules like Op-amps, Bandgaps, Data converters, LDO and PLL etc.

•                 Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,

•                 Knowledge of various analog layout techniques like matching, shielding etc.,

•                 Must have good communication skills and should be team player.

•                 Scripting and automation experience is a plus.

•                 Good communication skills, documentation, and presentation skills.

•                 Strong analytical and problem-solving skills.

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Qualifications

• BE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent

Behavioral skills required.

• Must possess strong written, verbal and presentation skills.
• Ability to establish a close working relationship with both customer peers and management.
• Explore what’s possible to get the job done, including creative use of unconventional solutions.
• Work effectively across functions and geographies
• Push to raise the bar while always operating with integrity.

Regards

Madhu

[email protected]