Lead Application Engineer

Posted 13 Days Ago
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Feldkirchen, Bayern, DEU
In-Office
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Serve as a technical advisor to semiconductor customers, lead evaluations and proofs-of-concept, provide deep expertise in power analysis and EM/IR signoff, deliver workshops and training, mentor junior engineers, collaborate with sales and R&D, and promote AI-assisted design methodologies and Cadence Digital Full Flow adoption.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title: Lead Application Engineer

Location: Feldkirchen (Munich), Germany

                                               

Reports to: Application Engineering Group Director

Job Overview:

As a Lead Application Engineer, you will serve as a trusted technical advisor to some of the world’s most innovative semiconductor companies, driving the adoption of Cadence’s Digital Implementation and Signoff solutions to help customers achieve industry-leading Power, Performance, and Area (PPA) results.

Working at the intersection of customer success and product innovation, you will shape how next-generation silicon is brought to market - leveraging the latest advances in AI-driven design technologies to accelerate design closure and solve complex implementation and signoff challenges.

You will also work directly with Cadence R&D to influence product direction, translating real-world customer needs into the features and tools that define the future of electronic design.

Job Responsibilities:

  • Lead customer evaluations, benchmarks, and proof-of-concept projects, guiding customers through complex technical decisions to accelerate design closure.
  • Provide deep technical expertise in Power Analysis, Electromigration/IR (EM/IR) Signoff, and advanced-node implementation methodologies across leading semiconductor processes.
  • Develop and deliver tailored customer presentations, technical workshops, and training sessions that build capability and confidence in Cadence’s Digital Full Flow.
  • Collaborate with sales teams to identify and qualify new business opportunities, translating technical insights into clear value propositions that drive technology adoption.
  • Mentor and develop junior Application Engineers, contributing to knowledge-sharing practices and raising the technical bar across the AE organisation.
  • Partner with R&D and Product Engineering to diagnose and resolve complex customer challenges and actively influence the product roadmap by communicating real-world customer requirements.
  • Evaluate and communicate the impact of AI-assisted design methodologies to customers, positioning Cadence’s AI-enabled and agentic design solutions as strategic differentiators.
  • Maintain up-to-date expertise in advanced nanometer implementation techniques and low-power design standards (UPF/CPF), ensuring customers benefit from current best practices.

Job Qualifications:

  • Degree in Electrical or Electronic Engineering, Microelectronics, or a related discipline or equivalent industry experience.
  • 5–8 years of experience in Physical Design, Digital Implementation, Signoff, or related semiconductor design disciplines.
  • Hands-on experience with Power Analysis and EM/IR Signoff (required).
  • Strong customer-facing communication skills and a structured approach to technical problem-solving.
  • Fluent English communication skills, both written and spoken.

Additional Skills/Preferences:               

  • Experience with Cadence Digital Full Flow tools including Innovus, Tempus, Voltus, and Joules
  • Advanced nanometer implementation experience
  • Familiarity with low-power design techniques and standards (IEEE 1801, UPF, CPF)
  • Experience working in or supporting customer-facing technical roles
  • Exposure to AI-assisted design methodologies

Additional Information:

  • Join a highly experienced and collaborative team of Application Engineers supporting leading semiconductor companies across Europe.
  • Play a key role in driving adoption of next-generation AI-enabled and agentic design solutions for some of the industry’s most advanced semiconductor customers.
  • Key stakeholders include customers’ design and engineering leads, Cadence R&D teams, and the European sales organisation.
  • Primary tools include Cadence’s Digital Full Flow suite: Innovus, Tempus, Voltus, Joules, and related implementation and signoff platforms.

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. 

Travel: Approximately 10% of travel is expected, primarily to support customer engagements and technical workshops across Europe.

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • Degree in Electrical or Electronic Engineering, Microelectronics, or related discipline or equivalent industry experience
  • 5-8 years of experience in Physical Design, Digital Implementation, Signoff, or related semiconductor design disciplines
  • Hands-on experience with Power Analysis and EM/IR Signoff
  • Strong customer-facing communication skills and structured technical problem-solving
  • Fluent English communication skills, written and spoken
  • Experience with Cadence Digital Full Flow tools (Innovus, Tempus, Voltus, Joules)
  • Advanced nanometer implementation experience
  • Familiarity with low-power design techniques and standards (IEEE 1801, UPF, CPF)
  • Experience in customer-facing technical roles
  • Exposure to AI-assisted design methodologies

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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