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Job Title: Lead Analog Layout Design Engineer (SERDES/UCie)
Location: Cork
Reports to: Sr Principal Engineer
Job Overview:
The Lead Analog Layout Design Engineer will take a Technical Leadership role on the PMA custom layout design team as part of a SERDES Product Team at Cadence Ireland.
Job Responsibilities:
- Design of High Speed SERDES for UCIe products at data rates up to 64 Gbps on leading edge technology nodes (e.g. 2nm FinFET CMOS)
- Design quality layouts of analog/mixed-signal circuit blocks, working in collaboration with circuit designers
- Responsibilities include all facets of the back-end flow, from initial floor planning through detailed layout and final verification of conformance to foundry design rules
- Participate in technical leadership of the team in the areas of layout design from block level to PHY top level integration and sign off
- Work with global teams (US, west coast and east coast), which work in different time-zones
Job Qualifications:
- Candidate’s background should include a minimum of 7 years of experience in CMOS SERDES or high-speed I/O IC layout design and development
- Proficient layout design experience in many of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators
- Implementing high speed and high accuracy cells, blocks and IP blocks in a timely fashion with high quality and efficiency
- Working with custom layout designers from groups all over the world to build high quality IP and test chips
- Working with circuit designers and project managers from groups all over the world to understand their technical and schedule needs
- Excellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment
- BEng, MEng or PhD
Additional Skills/Preferences:
- Cadence tool experience and design experience at >10Gbps and in <16nm technologies
- Collaborating with the Cadence R&D teams (Virtuoso, PVS developers) to help develop the layout editing and verification tools
- Interest in bringing changes to the analog/custom layout design paradigm
Additional Information:
Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
Travel: >10%
We’re doing work that matters. Help us solve what others can’t.Skills Required
- Minimum 7 years of experience in CMOS SERDES or high-speed I/O IC layout design and development
- Experience designing analog and mixed-signal circuit layouts
- Proficiency with SERDES circuit blocks including drivers, receivers, serializers, deserializers, phase interpolators, low-jitter PLLs, high-speed clock distribution, bias and bandgap circuits, and voltage regulators
- Experience implementing high-speed, high-accuracy cells, blocks, and IP blocks efficiently and with high quality
- Experience collaborating with global custom layout designers, circuit designers, and project managers
- Excellent problem-solving skills and analog aptitude
- Good communication skills and ability to work cooperatively in a team environment
- BEng, MEng, or PhD
- Cadence tool experience
- Design experience at data rates above 10 Gbps and in technologies below 16 nm
- Experience collaborating with Cadence R&D teams on Virtuoso and PVS development
- Interest in advancing analog and custom layout design methodologies
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
