Rivos

Junior Power-Management Architect

Posted 3 Days Ago

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2 Locations

Hybrid

1-3 Years Experience

Software

The Role

Join a hardware startup in Silicon Valley as a Junior Power-Management Architect focusing on modeling and optimizing Power/Performance features. Work with talented engineers to create designs for Accelerated computing platforms. Responsibilities include developing power management verification platform, collaborating with FW and SW teams, simulation, prototype validation, and more. BS/MS in CS/CE/EE required with 2-4 years of experience for BS and up to 2 years for MS. Strong programming skills and ability to work collaboratively in a dynamic environment.

Summary Generated by Built In

Join a cutting-edge and well-funded hardware startup in Silicon Valley as a Junior Power-Management Architect, focused on modeling and optimizing Power/Performance features on a cutting-edge design. Our mission is to reimagine silicon and create Risc-V based Accelerated computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

Responsibilities

As a Junior Power Management Architect, you will own or participate in the following:
Design and develop a power management verification and validation s/w platform that will be used as a testbed for analyzing existing power features and improving future revisions
Work closely with the FW and SW teams to integrate the platform into their environment for studying full-system power, current and thermal behavior
Perform extensive simulation and data analysis for varying system use cases
Prototype and validate new features in the platform with guidance from Architects and RTL engineers
Help in bring-up of internal silicon and collaborate with post-silicon teams to validate power-management specific HW and SW features.

Requirements

BS/MS degree in CS/CE/EE or equivalent experience
Experience with CPU/GPU/SoC architecture power and/or performance modeling using simulators
Good understanding of management features such as clock gating, power gating, DVFS is preferred
Solid programming skills in C/C++, Python
Working knowledge of Verilog, SystemVerilog for root-causing and triaging
Ability to work collaboratively in a fast-paced and dynamic environment
Go-getter capable of initiating and driving tasks from start to finish with minimum technical oversight

Education and Experience

BS (2 - 4 years of experience) or MS (up to 2 years of experience) with a degree in CS/CE/EE or equivalent field, The team already includes senior and mid-level engineers who will provide mentoring.