IP Logic Design Verification Engineer

Job Details:

Job Description: 

Seize the opportunity to work with the team responsible for RTL logic design and microarchitecture of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team is responsible for developing soft IPs, subsystems and gaskets for client and server chipsets.
This job requisition is to seek an experienced, disciplined and collaborative design verification engineer in Malaysia.
As a Chipsets Logic Design Verification Engineer, a typical day may include, but is not limited to:
Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure highquality integration and verification of the IP block. Drives quality assurance compliance for smooth IP SoC handoff.

Qualifications:The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent.

The candidate must have demonstrated the ability to solve technical problems with decent communication skills.

The candidate must also have demonstrated strong ethical standards.

Other technical requirements:
1+ years of relevant pre-silicon verification/logic design experience
1+ years of pre-silicon verification/logic design experience with various tools and methodologies including but not limited to: System Verilog, Python/Perl/Shell scripting, power-aware simulation with VCS/Synopsys tools, RTL model build.

Preferred Experience:
Experienced in developing test plan and contents and coverage points for validation purpose based on High Level Architecture specifications
Experienced in VLSI or Structural and Physical design flow and methodology, SIP and HIP interoperability validation.
Experienced in Power-aware design and validation flows.
Experienced in AMBA, UFS, SPI, USB, PCI express or any industry standard BUS protocol.
Strong chipset CPU level understanding required on power consumption, power estimation and low power design methods.
Experienced with various tools and methodologies including but not limited to: System Verilog for design and verification, Python/Perl/Shell scripting, logic simulators and debuggers from major EDAs, RTL model build and testbench development flow, performance verification, coverage based random constraint simulation, etc.

Job Type:College Grad

Shift:Shift 1 (Malaysia)

Primary Location: Malaysia, Penang

Additional Locations:Malaysia, Kulim

Business group:In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.