Integrated Circuit Layout Engineer

Great Sky is a technology startup based with a mission to rebuild AI from first principles. We are pursuing neuroscience-inspired hardware and algorithms that overcome the greatest challenges in scaling AI systems.

We’re seeking a highly motivated integrated circuit layout engineer to optimize superconducting electronic circuitry for Great Sky’s AI hardware platform.

Semiconductor IC layout experience is highly relevant for this role; prior superconducting electronics experience is not required. We will help you ramp on superconducting design rules, devices, and workflows. We are open to mid-level through senior candidates; title and scope will depend on experience.

The Challenge:

• Today’s AI systems are limited by data movement, latency, and energy efficiency. Great Sky is developing superconducting neural-network hardware that combines ultra-fast analog computation, local memory, and optical fan-out. Scaling this platform requires disciplined IC layout, verification, and tapeout execution across increasingly complex superconducting circuits.

Your Role:

• You will help us realize highly efficient superconducting circuit layouts on the path to massively scaled neural networks that enable inference with orders of magnitude speedups over the state of the art.

• Create layouts for individual superconducting device cells, reusable circuit blocks, and larger hierarchical structures such as neural-network circuits.

• Optimize layouts for area, parasitics, device performance, manufacturability, and scaling.

• Extension and improvement of our parametric/script-based layout engine to facilitate rapid scaling to even larger networks, using Python

• Support post-layout simulation and verification of passive and active superconducting circuits.

• Collaboration with the fabrication team and external foundries to ensure successful manufacturing of chips

• Deliver verified layouts for key superconducting device cells and reusable circuit blocks.

• Improve the reliability and scalability of our Python-based layout generation flow.

• Identify and implement meaningful area reductions in key device cells while preserving performance, manufacturability, and verification closure.

Required:

• Bachelor’s degree in electrical engineering, computer engineering, physics, or a related field, or equivalent practical experience.

• 3+ years of experience in integrated circuit layout engineering in semiconductor or superconducting device domains

• Experience with IC layout tools and formats such as Cadence Virtuoso, KLayout, Calibre, GDSII/OASIS, PCells, DRC/LVS, or similar workflows.

• Strong scripting ability in Python or a similar language, applied to parametric or automated layout generation

• Familiarity with post-layout extraction, parasitic-aware layout, or electromagnetic simulation workflows.

• Direct contribution to at least one successful IC tapeout, preferably involving hierarchical layout, custom devices, or nonstandard process constraints.

Preferred:

• Experience with development and customization of design rule check procedures for integrated circuit layouts

• Experience building or maintaining parametric cells, layout generators, or scripted layout flows.

• Experience with numerical analysis of superconducting circuits

• Experience managing large tapeouts with complex foundry processes

• Meaningful equity ownership in an early-stage deep tech company

• Employer-matched 401(k)

• Health, dental, vision, and life insurance

• Flexible PTO

• Support for ongoing learning, conference attendance, and skill development

Our culture is onsite by default (we're founded by scientists who are used to working in the lab), with flexibility for hybrid arrangements. For the right person and role, we're open to filling roles remotely