IC Verification Engineer

Posted 18 Days Ago
Be an Early Applicant
San Jose, CA
141K-225K Annually
7+ Years Experience
Semiconductor
The Role
The IC Verification Engineer will architect and develop a scalable Testbench environment, create test plans, debug regression failures, and lead documentation of the verification strategy. The role includes mentoring junior engineers and improving verification quality and efficiency.
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Job Description:

Job duties include:

·       Architect and Develop scalable and reusable Testbench Environment using the framework of Verification Methodologies.

·       Develop Test plans for all features of the design, conduct reviews, Write Functional coverage for these features.

·       Build pseudo-random tests to Verify the design and achieve full Functional coverage and stability of Regressions

·       Debug Regression failures, analyze Functional Coverage gaps and improve Tests to cover the gaps

·       Work with other members of the team, guide/mentor junior team members

·       Lead the documentation of Verification Strategy including Test plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design/architecture.

·       Come up with strategies to improve Verification quality and Efficiency

Mandatory Requirements:

·       Bachelor's degree in Electrical Engineering or related degree and 12+ years related experience or Master's degree in Electrical Engineering or related degree and 10+ years related experience

·       Decade+ experience in developing complex Verification Environments, developing Test plans, Functional coverage and pseudo-random testing

·       Must have gone through a full ASIC cycle right from Architecture development to Tapeout with full focus on Verification

·       Very proficient in System Verilog and Verification Methodologies like UVM

·       Good debug skills in analyzing regression failures and understanding of complex designs

·       A good understanding of a layered complex protocols like PCI Express or other multi-layered protocol

·       Work with the team and mentor junior engineers

These requirements are a plus:

·       Scripting knowledge of Python or Perl

·       Comfort with Makefiles

·       Experience with Verifying with other protocols like AXI

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $141,000 - $225,000.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Top Skills

System Verilog
The Company
HQ: San Jose, CA
38,985 Employees
On-site Workplace
Year Founded: 1991

What We Do

Broadcom Inc. (NASDAQ: AVGO) is a global technology leader that designs,
develops and supplies semiconductor and infrastructure software solutions.

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