IC Power, IR and EM Principal Application Engineer

Posted Yesterday
Be an Early Applicant
Austin, TX, USA
In-Office
Expert/Leader
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Lead development and support of chip power integrity, IR, and EM analysis tools and workflows. Solve electrical circuit and numerical/graph algorithm problems, model interconnects, package and die, write automation in Python/Tcl, and collaborate with EDA and semiconductor teams to drive IR/EM sign-off solutions.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

At Cadence, you have the opportunity to work with the dynamic and tenacious team solving some of the most complicated challenges in chip power integrity and thermal analysis. We are looking for people that are willing to push the boundaries of innovation to deliver highest quality solutions to our customers.

If tenacity, passion to innovate, determination to collaborate effectively, and win as a team are the attributes that define you, then you have a home in our team solving Power Integrity problems.

Ideal candidate should have:

  • Strong ability to solve electrical and electronic circuits.

  • Excellent knowledge on how power, IR, and EM analyses impact chip planning to IR/EM sign-off.

  • Fundamental understanding of interconnect modeling, package analysis, and die modeling.

  • Ability to write and debug automation code in Python or Tcl.

  • Solid grasp on foundational algorithms to solve numerical and graph problems.

  • Understanding of how EDA and Semiconductor industry eco-system works.

  • Alacrity to be an excellent team player.

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • Strong ability to solve electrical and electronic circuits.
  • Excellent knowledge on how power, IR, and EM analyses impact chip planning to IR/EM sign-off.
  • Fundamental understanding of interconnect modeling, package analysis, and die modeling.
  • Ability to write and debug automation code in Python or Tcl.
  • Solid grasp on foundational algorithms to solve numerical and graph problems.
  • Understanding of how EDA and Semiconductor industry eco-system works.
  • Alacrity to be an excellent team player.

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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