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Job Description:The descriptions are for layout engineers for our Library Group. Library Group is a part of Central Engineering Group.
In Library Group, we focus on circuit design for memory, I/O (Input/Output), and Standard Cells.
Requirements:
- Strong layout knowledge with a minimum of 3 to 4 years of experience
- Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools.
- Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm, 2nm, 1.4nm etc
- Experienced in digital (standard cell, memory, I/O) layout
- Experienced in analog layout is also a plus
Job Description:
- Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout
- Schedule time-line & layout floor-planning
- Complete quality layout and verification within planned schedule (without supervision for experienced engineer)
- Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team
Skill Set (Mem):
- Strong experience in memory layout design and physical verifications includes LVS, DRC, ERC, Antenna, Electro Migration in CMOS process.
- Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools.
- Good experience in Floor-planning, hierarchy layout and chip integration.
- Knowledge of Script Programming and SKILL Programming would be a plus.
- Able to lead or train a team of junior engineers
- Good knowledge on memory layout topology.
- Experience in memory compiler will be a plus.
- Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines.
- Self-reliant, with ability to work independently as well as a team.
- Good leadership quality on project management.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Skills Required
- Minimum 3-4 years strong layout experience
- Cadence layout tools and Cadence schematic capture experience
- Experience with Calibre and Hercules verification tools
- Strong layout knowledge in submicron process nodes (e.g., 16nm, 7nm, 5nm, 3nm, 2nm, 1.4nm)
- Digital layout experience (standard cell, memory, I/O)
- Memory layout design and physical verification (LVS, DRC, ERC, Antenna, Electromigration)
- Experience with Cadence Virtuoso (XL, VXL or EXL)
- Floor-planning, hierarchy layout and chip integration experience
- Ability to lead or train a team of junior engineers
- Knowledge of memory layout topology
- Ability to lead new technology reviews and document layout methodology, flow and guidelines
- Self-reliant; able to work independently and within a team
- Good leadership and project management skills
- Analog layout experience
- Script programming and SKILL programming
- Experience in memory compiler
Broadcom Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Broadcom and has not been reviewed or approved by Broadcom.
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Equity Value & Accessibility — Equity is used broadly through RSUs with quarterly or annual vesting, and an ESPP with a discount and look‑back that can add meaningful upside. Company disclosures show ongoing equity grants, including inducement RSUs tied to acquisitions, underscoring equity’s central role in total rewards.
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Retirement Support — A 401(k) plan with a competitive company match and immediate vesting is consistently highlighted, supporting long‑term savings. Tax‑advantaged accounts like HSA/FSA further strengthen the financial wellness toolkit.
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Pay Growth & Progression — Compensation ceilings in technical tracks are described as high, with wide ranges and very strong totals for experienced engineers. Sales compensation is also characterized as competitive, supporting attractive on‑target earnings.
Broadcom Insights
What We Do
Broadcom Inc. (NASDAQ: AVGO) is a global technology leader that designs, develops and supplies semiconductor and infrastructure software solutions.





