IC Implementation, Sr Principal AE

Reposted 3 Days Ago
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San Jose, CA, USA
In-Office
148K-276K Annually
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Leads advanced-node digital IC implementation engagements across pre-sales and post-sales customer projects. Drives synthesis, place-and-route, clock-tree synthesis, floor planning, timing closure, signoff, and power optimization at 3nm and below. Develops TCL, Perl, and Python automation solutions, resolves complex design issues, partners with sales, and mentors engineers. Requires extensive physical implementation experience, multiple tapeouts, strong communication, and technical leadership.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description Summary

The Senior Principal Application Engineer will be a trusted technical leader, driving complex pre-sales and post-sales engagements for Cadence Digital IC products at advanced nodes. This role demands a proven ability to solve the toughest design challenges and deliver innovative solutions that ensure customer success.


Key Responsibilities

  • Lead technical strategy and execution for critical customer design projects, influencing design methodologies and implementation flows at advanced nodes (3nm and below)
  • Partner with sales teams to grow Cadence business by showcasing Cadence’s leadership in digital implementation.
  • Serve as a primary consultant for advanced-node design synthesis & implementation, Agentic-AI and signoff, leveraging deep expertise in synthesis, place & route, CTS,  floor planning, timing signoff, design convergence with timing closure, and power optimization as key aspects.
  • Develop and deploy custom solutions using scripting languages (TCL, PERL, Python) to address unique customer requirements.
  • Mentor and guide junior engineers, fostering technical excellence and knowledge sharing across teams.

  • Requirements
  • 12+ years of hands-on experience in physical implementation and signoff at 7nm and below, with multiple successful tapeouts.
  • Demonstrated expertise in digital synthesis, place-and-route, static timing analysis, AI in EDA, and achieving timing and power goals for advanced node designs.
  • Strong debugging skills with the ability to isolate and resolve critical design issues efficiently.
  • Proficiency in scripting for automation and flow customization.
  • Bachelor’s or Master’s in Electrical/Computer Engineering.

Exceptional communication and leadership skills, with a track record of building

The annual salary range for California is $148,400 to $275,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • 12+ years of hands-on experience in physical implementation and signoff at 7nm and below
  • Multiple successful tapeouts
  • Expertise in digital synthesis, place-and-route, static timing analysis, AI in EDA, and advanced-node timing and power optimization
  • Strong debugging skills for isolating and resolving critical design issues
  • Proficiency in scripting for automation and flow customization using TCL, Perl, or Python
  • Bachelor's or Master's degree in Electrical or Computer Engineering
  • Exceptional communication and leadership skills
  • Track record of building and mentoring technical capabilities

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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