IC Design Engineer

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We are seeking a highly motivated and experienced Senior DFT Engineer to join our WIFI team. In this role, you will architect and implement advanced DFT solutions for cutting-edge SoCs, ensuring high test coverage and efficient silicon debug. You will be instrumental in developing robust test strategies and collaborating across functional teams from RTL design to post-silicon validation.

Job Requirements

• a BS in EE/EECS with 9-12+ years of experience or an MS in EE/EECS with 6-9+ years of experience
• Own and drive DFT architecture and implementation for complex SoCs and IPs.
• Develop and integrate DFT features such as:
  • Scan insertion and compression (e.g., LBIST/MBIST).
  • Boundary scan (IEEE 1149.x JTAG).
  • At-speed testing (transition delay, logic BIST, etc.).
  • Memory BIST and redundancy repair flows.
• Manage RTL-level and gate-level DFT integration.
• Work with RTL, STA, Synthesis, and Physical Design teams to ensure testability is achieved with minimal area/timing impact.
• Generate and validate test patterns (ATPG, MBIST) using industry-standard tools.
• Debug test pattern issues in silicon and during ATE bring-up.
• Drive post-silicon validation and yield enhancement initiatives.
• Familiar with Mentor-Tessent flow is a plus.
• Skilled in scripting languages (TCL, Perl, Python, Shell) for automation.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

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