Broadcom

IC Design Engineer (DFT)

Reposted 2 Days Ago

Be an Early Applicant

Zhangjiang, Shanghai Municipality, Shanghai

Mid level

Semiconductor

The Role

The role involves defining DFT architecture, implementing DFT schemes, verifying DFT logic, and debugging DFT patterns on ATE with a focus on DFT methodologies.

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Job Description:

Responsibilities:

Participate in chip level DFT architecture definition.
Implement DFT schemes, including scan, boundary scan, Mem BIST and Logic BIST.
Verify all DFT logics and test patterns with simulation
Test modes static timing analysis
Participate in ATE bring-up and debug the DFT patterns on ATE.

Requirements/Qualifications:

Good understanding of the General DFT methodology such as BIST, SCAN, JTAG, ATPG and SSN
Be familiar with Mentor / Synopsys DFT flow and tools
Experience in developing constraints for synthesis/STA
Multi-mode, multi-corner STA experience in 16nm and lower technology nodes, Understanding Sign-Off Checks
Experience in silicon debug, diagnosis and yield improvement

Education/Certifications
Preferred Degree: MS Preferred Major: Microelectronics or related discipline

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

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