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Job Description:We need an engineer to own the end-to-end silicon diagnostic pipeline. You won’t just be looking at reports; you will be building the engines that generate them. In this role, you will ingest massive volumes of scan failure data and process parameters, using AI-driven methodologies to find the "needle in the haystack" that is hindering our yield.
Your goal is simple but ambitious: Use AI/ML to transform millions of data points into actionable insights that drive aggressive yield ramps and shorten time-to-market.
Key ResponsibilitiesAI-Driven Debug: Develop and deploy ML models to automate the classification of scan failures (Chain, Stuck-at, Transition) and correlate them with design-for-test (DFT) structures.
Predictive Yield Modeling: Integrate high-dimensional data—including Fab process parameters, PCM (Process Control Monitoring), and E-test data—to predict yield excursions before they hit the assembly line.
Holistic Yield Analysis: Look beyond the bitcell. You’ll analyze the interplay between design marginalities, voltage scaling, and manufacturing variations.
Tool Orchestration: Evaluate and implement cutting-edge AI-based EDA tools for root-cause analysis and systematic defect identification.
Cross-Functional Leadership: Act as the "translator" between the Fab, Design, and Test teams, using data to prove where the silicon is diverging from the simulation.
ASIC Design Engineering: Deep understanding of ASIC design, including logic circuits, memory, PLL/Analog, Place and route, STA, DFT, DFM, etc.
The Debug Specialist: You know your way around scan compression, BIST, and ATPG patterns. You understand what a "shmoo plot" is telling you about a timing marginality.
The Data Scientist: You don't just "use" tools; you understand the math. You are proficient in Python (Pandas, Scikit-Learn, PyTorch/TensorFlow) for building custom analysis pipelines.
The Yield Strategist: You have a deep understanding of semiconductor manufacturing processes (FinFET nodes) and how physical defects manifest as logical failures.
Bachelor's degree plus 8+ years of related experience OR Master's degree plus 6+ years of related experience
3+ years in Silicon Debug, DFT, or Yield Engineering.
Knowledge of Deep Sub-micron (FinFET) effects, including IR drop, crosstalk, and process variation
Experience with Pattern Recognition, Clustering (for defect binning), and Regression models.
Expertise in Python, SQL, and big data environments (Spark, Snowflake, etc.).
Familiarity with industry-standard yield management systems (e.g., PDF Solutions, Synopsys YieldExplorer, or Cadence Clarity).
Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $108,000 - $192,000
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Skills Required
- Bachelor's degree plus 8+ years experience OR Master's degree plus 6+ years experience
- 3+ years in Silicon Debug, DFT, or Yield Engineering
- Deep understanding of ASIC design (logic circuits, memory, PLL/Analog, place and route, STA, DFT, DFM)
- Experience with scan compression, BIST, ATPG patterns and interpreting shmoo plots
- Knowledge of deep sub-micron (FinFET) effects including IR drop, crosstalk, and process variation
- Proficiency in Python (Pandas, Scikit-Learn, PyTorch/TensorFlow) for custom analysis pipelines
- Expertise in SQL and big data environments (Spark, Snowflake)
- Experience with pattern recognition, clustering (defect binning), and regression models
- Familiarity with industry yield management systems (PDF Solutions, Synopsys YieldExplorer, Cadence Clarity)
- Ability to lead cross-functional interactions between Fab, Design, and Test teams
Broadcom Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Broadcom and has not been reviewed or approved by Broadcom.
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Equity Value & Accessibility — Equity is used broadly through RSUs with quarterly or annual vesting, and an ESPP with a discount and look‑back that can add meaningful upside. Company disclosures show ongoing equity grants, including inducement RSUs tied to acquisitions, underscoring equity’s central role in total rewards.
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Retirement Support — A 401(k) plan with a competitive company match and immediate vesting is consistently highlighted, supporting long‑term savings. Tax‑advantaged accounts like HSA/FSA further strengthen the financial wellness toolkit.
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Pay Growth & Progression — Compensation ceilings in technical tracks are described as high, with wide ranges and very strong totals for experienced engineers. Sales compensation is also characterized as competitive, supporting attractive on‑target earnings.
Broadcom Insights
What We Do
Broadcom Inc. (NASDAQ: AVGO) is a global technology leader that designs, develops and supplies semiconductor and infrastructure software solutions.
