Design High-Speed Interface Controller IP
Test, Performance analysis in IP/chiptop level (bus, memory bandwidth) simulation
Test, Debugging & Troubleshooting of Silicon
Minimum Qualifications
Good knowledge and understanding in Interface protocol (e.g bus or high-speed interface with flow control, retransmission scheme, etc.)
Experience in RTL design and logic synthesis, verification, timing closure
Good knowledge and experience of buffer, CDC design required for Interface Design.
Preferred Qualifications
Excellent understanding in High-Speed Interface standard specifications (e.g PCIe, LPDDR, HBM, Ethernet or UCIe, etc.)
High understanding of High-Speed interface technology e.g. SERDES, Channel encoding, OSI-7 layer, Equalization, etc.
Skills Required
- Good knowledge and understanding in Interface protocols
- Experience in RTL design and logic synthesis
- Good knowledge of buffer and CDC design for Interface Design
What We Do
FuriosaAI designs and develops data center accelerators for the most advanced AI models and applications. Our mission is to make AI computing sustainable so everyone on Earth has access to powerful AI. Our Background Three misfit engineers with each from HW, SW and algorithm fields who had previously worked for AMD, Qualcomm and Samsung got together and founded FuriosaAI in 2017 to build the world’s best AI chips. The company has raised more than $100 million, with investments from DSC Investment, Korea Development Bank, and Naver, the largest internet provider in Korea. We have partnered on our first two products with a wide range of industry leaders including TSMC, ASUS, SK Hynix, GUC, and Samsung. FuriosaAI now has over 140 employees across Seoul, Silicon Valley, and Europe. Our Approach We are building full stack solutions to offer the most optimal combination of programmability, efficiency, and ease of use. We achieve this through a “first principles” approach to engineering: We start with the core problem, which is how to accelerate.
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