Welcome to Codasip
We believe is the most innovative processor solutions company. We take pride in designing and developing cutting-edge, high-performance, and energy-efficient CPU cores from scratch, and our own automated proprietary tools to fully customize them. We give our customers a unique competitive advantage by empowering their system-on-chip developers to build the most innovative products.
Our processor cores are based on the RISC-V open architecture. The potential for customizing RISC-V is unlocked with the Codasip Custom Compute approach: our unique architecture description language, CodAL, and the powerful automated processor design tool, Codasip Studio. These are at the heart of our unique and groundbreaking RISC-V processor solutions.
Founded in 2014, we've grown into a thriving and talented global community. Our IP engineering teams work from offices spread across Europe, including our first and largest design center in the beautiful city of Brno, Czechia. Across Europe, we already have design teams in Cambridge, Bristol, Munich, Villeneuve-Loubet, Barcelona, Thessaloniki, Heraklion and Athens. The Codasip team is also based close to its customers, which means we have dedicated sales and application engineers in the USA, Japan, Korea, and China.
Codasip is a private company backed by well-funded EU grants. Our products are already making a real impact, with billions of devices already in the market powered by our processor IP and tools.
Requirements
HLS TEAM IS PRIMARILY FOCUSED ON:
- The tool, that automatically generates microprocessor hardware representation in SystemVerilog from the definition in CodAL language
- Integration of the output with the third-party EDA tools (RTL simulators, linters, synthesizers)
- On-chip debugging support – contributing to the OpenOCD open-source project and integrating it to our solution
- Maintenance and development of the example CPU designs
YOUR CORE RESPONSIBILITIES WILL BE:
- Participation on the analysis and preparation of new features
- C++ development mostly in 14/17 standard
- Checking the integrity of generated output (SysVerilog) with the third-party EDA tools
- Maintenance and development of the example and testing CPU designs
YOU SHOULD HAVE:
- Great knowledge of C++
- Basic knowledge of at least one HDL language (VHDL/Verilog/SystemVerilog)
- Analytical thinking, self-sufficiency, and openness to team collaboration
- English on the communication level
NICE-TO-HAVES:
- Passion for hardware development
- Knowledge of versioning tools (Git, SVN)
- Knowledge of scripting languages (Python, Tcl)
- Experience with HW development and verification
- Experience with microcontroller programming (e.g. AVR/PIC/ARM/..., JTAG, OpenOCD)
Benefits
Want to be an architect of ambition? Join Codasip
At Codasip we are committed to fostering a creative and collaborative work environment. Codasippers have the freedom to explore original ideas and experiment with new techniques. We believe in the benefits of cross-departmental collaboration and encourage sharing to build awareness throughout the teams. This enables you to add value through variety in your work.
When you join Codasip, you become part of a motivated team of self-starters where your ideas are appreciated and your voice is heard. We strive to create an environment where your ambition can flourish and your career can reach new heights. So, come and join our team of architects of ambition. We can't wait to see what you'll achieve at Codasip.
SOME USEFUL LINKS ON CODASIP:
- Codasip RISC V Processor Solutions
- Velký technologický úspěch. Česko povede vývoj evropského počítačového procesoru
- www.zvut.cz
- Codasip board initiates an expedited process to sell the company
Top Skills
What We Do
Codasip is a processor solutions company which helps developers to differentiate their products. We are Europe’s leading RISC-V company with a global presence. Billions of chips already use our technology.
In today’s technology market, differentiation is everything. The difference between success and failure. And, in chip design, this difference is quite literally wafer thin. With increasing transistor costs, your developers can no longer rely on semiconductor scaling and legacy processors to achieve your goals. The only way forward is to implement custom compute with designs tailored to your applications.
We deliver custom compute through the combination of the open RISC-V ISA, Codasip Studio processor design automation and high-quality processor IP. Our innovative approach lets you easily customize and differentiate your designs. You can develop high-performing, and game-changing products that are truly transformational.
Founding member of RISC-V International.
Founding member of the CHERI Alliance.
