In this position, you will be involving in the training, design and development of next generation SOC/CPU for wide range of Intel products. Your responsibilities will include some of the following but not limited to:
Assist design unit owner in Register Transfer Level RTL model functional validation. Use CAD tool extensively to simulate logic behavior and circuit performance and direction of physical design for next generation, deep sub-micron embedded circuit solutions. Verify the circuit behavior against the original simulation model and first silicon.
Define VLSI Structural Design methodology and developing design flows. Implement structural physical designs, such as synthesis, floor planning, power-grid and clock tree designs, timing budgeting and closure, place and route, RC-extraction and integration. Verify structural physical designs, such as functional equivalency, timing/performance, noise, layout design rules, reliability and power.
Develop Analog IP on next generation deep submicron process for the Intel's SOC, perform tasks related to Very-large-scale integration VLSI complementary metal-oxide-semiconductor CMOS IC design, Solid state physics and physical layout. Such tasks may include: Circuit design of high speed clocking related circuits [phase-locked loop PLL, delay-locked loop DLL, bandgap] or high voltage input/output IO [double data rate DDR/LPDDR, General-purpose input/output GPIO, OPIO].
Responsible for Integration of Third party IPs -- Synthesis, functional and/or timing convergence, and pre and post-si debug of IPs developed by various external vendors as well as within the company. Handling of signals crossing power planes and clock domains, industry standard protocols including hardware and software details dealing with Memory LPDDR, storage eMMC, SATA, UFS, peripherals PCIe, USB, and MIPI interfaces in SOC devices. System integration dealing with Si/ Platform/ FW/ MW/ drivers/ OS/ Apps on Android Windows-based tablets and phones.
You must possess a Bachelor of Engineering degree or a Master of Science degree in Electronic, Electrical or Computer Engineering.
Additional qualifications include:
Familiarity with Very Large Scale Integration VLSI Complementary Metal-Oxide Semiconductor CMOS logic circuit design
Well versed in UNIX, C programming and relevant Computer Aided Design CAD tools.
Job Type:Intel Contract EmployeeShift:Shift 1 (Malaysia)Primary Location: Malaysia, PenangAdditional Locations:Malaysia, KulimPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Bachelor or Master degree in Electronic, Electrical, or Computer Engineering
- Familiarity with VLSI CMOS logic circuit design
- Experience with RTL functional validation and simulation using CAD tools
- Knowledge of structural physical design flows: synthesis, floorplanning, power-grid, clock tree, timing closure, place and route, RC extraction
- Analog IP design knowledge (PLL, DLL, bandgap, high-speed IO) and deep-submicron CMOS circuit design
- Experience with memory and peripheral interfaces: DDR/LPDDR, eMMC, SATA, UFS, PCIe, USB, MIPI
- Proficiency with UNIX and C programming
- Ability to integrate and debug third-party IP, and perform pre- and post-silicon debug and system integration
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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