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The Role
Designs and develops RTL for GPU media IP, including encoder and decoder logic. Defines architecture and microarchitecture, performs simulation and unit-level verification, and optimizes designs for power, performance, area, timing, and physical implementation. Develops behavioral models in C or Perl, debugs hardware simulations, supports SoC integration, and uses AI-assisted tools for specification, RTL generation, and verification.
Summary Generated by Built In
Job Details:Job Description: GPU Senior Logic Design Engineer:
Develop logic design, generate/write Register Transfer Level (RTL) code, and perform simulation for Media IP components. This includes generating essential components such as libraries and functional units and delivering complete IP blocks for full chip design integration. Participate in the definition of architecture and microarchitecture features of the block being designed. Apply various strategies, tools, and methods to generate/write RTL and optimize the logic to meet power, performance, area, timing goals, and design integrity for physical implementation. Review the verification plan and the implementation to ensure design features are correctly verified across verification hierarchies. Drive unit level verification and implement corrective measures for failing RTL tests to ensure feature correctness. Supports SoC customers to ensure high-quality integration of Media IP block. Your contributions will directly impact Intel's ability to deliver innovative graphics technologies to our customers, helping shape the future of computing
Business group: Intel's Media HW Engineering team
Key Responsibilities
• Conduct feature feasibility studies, performance analysis, and microarchitecture design based on landing zone requirements
• Design a wide variety of digital logic functions with the emphasis on media encoder/decoder design
• Develop, implement, and validate Register Transfer Level (RTL) design
• Perform power, performance, area, and timing optimization to meet design goals
• Developing C or Perl behavioral models to support RTL functionality verification
• Utilize AI models to enhance specification development, RTL code generation, and verification collateral creationQualifications:Education and Experience
• Bachelor's degree in Computer Engineering, Electrical Engineering, or a related field with 8+ years of industry experience in RTL design and logic development with expertise in System Verilog.
OR
• Master's degree in Computer Engineering, Electrical Engineering, or a related field with 6+ years of industry experience in RTL design and logic development with expertise in System Verilog.
Required skills and experience
• Computer system architecture
• Digital electronics and logic design
• Verilog or System Verilog
• Logic verification, synthesis, and timing analysis tools
• C, Perl, and Python programming
• AI-assisted ASIC Design and Verification tools.
Preferred skills and experience
• Knowledge of video codec standards such as H.264, HEVC, VP8/9, AV1, VVC, and other popular codecs
• Advanced knowledge of microarchitecture fundamentals and logic design verification methodologies.
• Strong communication, collaboration, and problem-solving skills
• Self-motivated and self-directed, with the ability to work effectively both independently and as part of a team
• Proven ability to effectively debug microarchitecture and hardware simulations.
Job Type:Experienced HireShift:Shift 1 (India)Primary Location: India, BangaloreAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Bachelor's degree in Computer Engineering, Electrical Engineering, or a related field and 8+ years of industry experience in RTL design and logic development
- Master's degree in Computer Engineering, Electrical Engineering, or a related field and 6+ years of industry experience in RTL design and logic development
- Expertise in SystemVerilog
- Computer system architecture
- Digital electronics and logic design
- Verilog or SystemVerilog
- Logic verification, synthesis, and timing analysis tools
- C, Perl, and Python programming
- AI-assisted ASIC design and verification tools
- Knowledge of video codec standards including H.264, HEVC, VP8/9, AV1, and VVC
- Advanced knowledge of microarchitecture fundamentals and logic design verification methodologies
- Ability to debug microarchitecture and hardware simulations
- Strong communication, collaboration, and problem-solving skills
- Ability to work independently and as part of a team
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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The Company
What We Do
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