GPU Physical Design Engineer Lead

Job Details:

Job Description: 

The primary responsibilities for this role will include, but are not limited to:

• In this position, the candidate will be part of a team implementing ASIC designs for Integrated/Discrete Graphics and AI SoCs on leading edge process technology and EDA tools.
• The team is responsible for all SoC level physical design and optimization flows ranging from Floor-planning, Clocking, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN verification, Quality Assurance, Layout Verification etc.
• Responsibilities may also include defining design requirements such as frequency, operating voltages, power, etc. to achieve optimized designs on new technologies, processes and architectures. 
•  The candidate would be required to work closely with the rest of the project team members to resolve issues which arise during the design cycle and take the key learnings into the next product cycle.

A successful candidate will have proven experience demonstrating the following skills and behavioral traits:

• The ideal candidate will be capable of leading a small team as well as interacting with architecture and design teams to improve IP and ultimate product quality and performance.
•  Good leadership and communication skills are necessary due to the nature of the work, size and complexity of the products and the size of the team.

Qualifications:

Minimum Qualifications:

Minimum qualifications are required to be initially considered for this position. Requirements listed would be obtained through a combination of industry-relevant job experience, internship experience and or schoolwork/classes/research.

• Bachelor’s in Electrical/Computer Engineering with 9+ years relevant work experience, or Master's in Electrical/Computer Engineering with 6+ years relevant work experience.
• Experience in: Logic Design, VLSI/ASIC Design, Computer Architecture.
• Current Industry Experience in one or more ASIC style design flows – floorplanning, clock construction, synthesis, place and route, static timing analysis, layout verification.
• Experience with Unix/Linux, Perl and TCL in order to implement useable, flexible cshell/perl/tcl programs that automate tool/flow methodologies.

Preferred Qualifications:

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates

• Preferred Experience in SoC integration methodologies including floorplan/timing integration of a variety of blocks into an SoC design.
• Preferred Knowledge of Clock Construction Methodology and Power estimation/optimization.

          

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, California, Folsom

Additional Locations:US, California, Santa Clara

Business group:At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $190,610.00-269,100.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.