Full Chip Timing Modeling and Integration Engineer

Job Details:

Job Description:

• Altera is seeking highly qualified candidates to join our Full Chip Timing team. Altera continues to deliver industry-leading (FPGA) Field-Programmable Gate Array solutions to customers.
• As a Full Chip Engineer, you will be developing timing methodologies and executing full-chip timing for Altera’s next generation product lines in the world's most advanced process technologies.
• This will be a fast-paced dynamic environment where you will be part of a high-performance design team working toward next generation FPGA products.
• You will work in a hands-on capacity performing full chip timing analysis.
• You will utilize your extensive design experience and interpersonal skills to efficiently solve technical issues, drive continuous improvement, negotiate, and clearly communicate technical trade-offs with a diverse cross-functional and multi-site team.
• Experienced to work to aggressive schedules as part of a team and independently.
• Your role will include, but not limited to: Design and Architecture understanding.
• Interaction with Front End and Back End teams, clocking and constraints development.
• Understanding extraction issues, design margins, timing signoff and quality checks.
• Be part of debug and troubleshooting for a wide variety of tasks up to and including difficult, critical design issues and proactive intervention.
• You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position.

• collaborate with cross-functional teams to define timing modeling strategies and solutions, generate high level timing models, integrate and validate timing models.

• Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

   

Qualifications:

Minimum Required Qualifications:

• BS/MS Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
• 5+ years of relevant experience should include:
• Experience in SoC development
• Experience with advanced process nodes
• Industry standard timing formats such as Liberty, Verilog, and Design Constraints (SDC).
• Static Timing Analysis (STA) / Correlating STA results with Spice.
• Timing modeling and library QA.
• Experience in Script writing for design automation in Python and Tcl
• Silicon modeling concepts (e.g. AOCV, POCV).

Additional Preferred Qualifications:

• 7+ years of SoC Development / Timing Lead Experience
• Experience in the completion of several complex multi voltage domain
• Experience with common modes of operation, including functional and DFT, for use in constraint review and management.
• Having experience in architecture and/or design of: FPGA, DDR, PCIe, Ethernet, HBM

Job Type: Regular

Shift:Shift 1 (Malaysia)

Primary Location:Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.