Develops the verification plan to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Supports SoC customers to ensure high-quality integration and verification of the IP block.
Drives quality assurance compliance for smooth IP-SoC handoff.
• BS/MS or PhD in Electronics Engineering
• Strong in communication, leadership, investigation, problem solving & analytical skill
• Proficiency with RTL coding using HDL language(s). Familiarity with logic simulation and debug environments
• Knowledge of scripting is an advantage
Job Type: RegularShift:Shift 1 (Malaysia)Primary Location:Penang 15, Penang, MalaysiaAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
What We Do
Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.
