FPGA IP Design Engineer

Job Details:

Job Description:

Altera's IP Solutions Engineering (IPSE) team develops comprehensive solutions to provide customers easy and efficient access to the capabilities of Intel's FPGA devices. These solutions are provided as highly configurable intellectual property IP cores that are fully integrated with Altera's software CAD tool, Quartus Prime.

We build IP cores for customized chip-to-chip interfaces such as high-speed ADC/DAC tiles or leading-edge transceiver interfaces to enable Ethernet, PCIe, and other protocols.

Another set of IP cores we build are to enable Memory Subsystems using External Memory Interfaces (like DDR5, LPDDR5) or High Bandwidth Memory (HBM) over a high-speed NOC.

These IP cores provide configurable access to these high-speed, high-bandwidth memory devices, chip-to-chip interfaces, and transceiver protocols. Most customers require some form of packet processing, storage or buffering, and thus, these IP cores become a critical component of most electronic systems.

The constantly rising speed and complexity of memory devices, chip-to-chip, and transceiver interfaces presents a challenging design problem that requires system level knowledge of silicon, software, IP, and customer applications.

As an IP Design Engineer, you will work with a team of engineers to develop and verify state-of-the-art Memory Interface, chip-to-chip, or transceiver-based IP cores. You will be working on advanced device architectures, design definition, implementation, and verification. You will also be developing design examples and simulation models, accompanied by a rich set of technical documentation.

Your specific responsibilities will include, but are not limited to the following:

• Architecture and Design based on the latest protocol specifications for memory, chip-to-chip, or transceiver interfaces RTL development

• Device support and CAD tool integration

• Verification (e.g. verification IP, methodologies, frameworks, bus functional models, regression tests)

• Hardware power-on and debug

• New product release and rollout support

• Customer technical support

The candidate should possess the following behavioral traits:

• Strong skills in communication, initiative, innovation, and teamwork

• Highly motivated to learn and adapt to fast-changing technologies and environments

• Excellent problem-solving skills and attention to detail

• Demonstrate fundamental values such as accountability, integrity, and a winning mindset

• Collaborative mindset, strong influencing skills, and a willingness to work across geographical locations.

Qualifications:

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

 

Minimum Qualifications:

• BS degree or MS degree in Computer Engineering, Engineering Science, Electrical Engineering, Computer Science or equivalent

• 3+ years of experience in Digital logic hardware (e.g. SystemVerilog, Verilog and/or VHDL) design or verification

• 3+ years of experience in Software programming or scripting (e.g. C/C++ and/or Python)

 

 

Preferred Qualifications:

• 4+ year of experience with IP Integration, RTL Design, SystemVerilog, Verilog and/or VHDL

• 4+ year of experience with software programming and/or scripting languages (e.g. C/C++ and/or Python)

• FPGA design experience

• Experience with RTL simulation, timing closure, STA

• Experience with Memory Interfaces, High-speed ADC/DAC, or Transceiver Protocols (e.g. Ethernet, PCIe)

Job Type: Regular

Shift:Shift 1 (Canada)

Primary Location:Toronto, Ontario, Canada

Additional Locations:

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.