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This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodations do not pose an undue hardship.

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Sr ASIC Implementation Engineer

Role/Responsibilities• As the physical implementation lead you will set up the flow for both logic and physical synthesis flow for various technology nodes.• Work with the ASIC design and DFT teams to understand the design and help review or create timing constraints.• Check the RTL design for clean synthesis run, perform STA and LEC on netlist.• Work with RFIC teams to make sure the top-level integration of analog blocks is done properly and correct by construction, including formal connectivity checks.• Work with P&R teams to ensure a smooth hand off netlists, ensure the timely execution of the P&R responsibilities by that team.• Participate in flow reviews of all the blocks with the P&R team to ensure that they achieve the best PPA for all blocks.• Lead the timing sign-off for the post P&R database.• Ensure that the chip meets the required DFM criteria by verifying the IR/EM results.

BASIC QUALIFICATIONS• Bachelor's degree in Electrical / Communications Engineering or related field, or equivalent experience.• 10+ years of experience in ASIC implementation, i.e., synthesis, STA and working with P&R for deep sub-micron nodes, preferably 16nm or smaller.• Experience leading or solely developing the methodology and scripts for physical synthesis.• Proven track record in taping out chips that have gone into high volume production.• Familiar with implementing chips that have multiple power islands and power gating.

PREFERRED QUALIFICATIONS• Master's or Ph.D degree in Electrical / Communications Engineering.• 10+ years of experience in ASIC implementation.• Experience in leading physical design.• Strong exposure to UPF flow for low power design.• Strong written and verbal skills• Experience of working in multi-site/multi-team environment