Design Engineer - STA

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

We are Silicon Labs. We are the leading provider of silicon, software and solutions for a smarter, more connected world. We hire the most innovative talent in the world to solve the industry’s toughest problems, providing our customers with significant advantages in performance, energy savings, connectivity and design simplicity. Silicon Labs’ software and mixed signal engineering teams create solutions for customers in diverse markets including the Internet of Things, (IoT), internet infrastructure, TV tuners, as well as automotive and consumer radios. Our solutions are in products from the market leaders in home automation, electric vehicles, green technology, smart TVs and home voice control automation. We take pride in our products and in our people, and that’s one of the many reasons we continue to be awarded Most Respected Public Semiconductor Company by the Global Semiconductor Alliance

• Job Description:

We are looking for a skilled Static Timing Analysis (STA) Engineer with 2–4 years of experience to contribute to the development and sign-off of high-performance SoCs and ASICs. The ideal candidate will have hands-on experience with STA flows, timing constraints, and timing closure techniques across various PVT corners and operating modes.

• Experience Level:

2-4 years

• Education Requirements:

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, or related fields

• Key Responsibilities:
  • Own STA execution for digital blocks or top-level across multiple corners and modes
  • Develop, validate, and maintain SDC constraints for RTL-to-GDSII flow
  • Analyze setup/hold violations and partner with RTL, synthesis, and physical design teams to close timing
  • Generate and interpret timing reports using tools like PrimeTime or Tempus
  • Work on timing ECOs to fix critical paths or slack issues
  • Participate in defining and improving timing methodology and automation scripts
  • Perform timing checks for clock domain crossings (CDC) and false/multicycle paths

• Required Skills:
  • 2–4 years of relevant experience in STA for ASIC or SoC development
  • Strong command of timing fundamentals including PVT variations, clocking schemes, and timing exceptions
  • Proficiency with tools like Synopsys PrimeTime or Cadence Tempus
  • Experience in writing and debugging SDC constraints
  • Scripting knowledge in TCL/Perl/Python for automation of STA tasks
  • Exposure to synthesis, floorplanning, placement & routing is a plus
  • Good debugging, communication, and cross-functional collaboration skills

Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.