Engineer I-Verification

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Job Description:

Join our international team of verification experts in San Jose, CA to verify the next generation of RISC-V based System on a Chip (SOC) semiconductor products integrated into state of art FPGA architectures. You will be part of the team that develops the SOC products, which will be used in leading electronic systems. You will be working with leading-edge verification tools and methodologies to verify our state of-the-art products. You will have an opportunity to understand in depth knowledge of FPGA and SOC architectures. You will work closely with silicon design engineers and logic design and verification engineers to perform all the aspects of verification. You will be using the state-of-art verification methodologies and EDA tools for logic verification.

Job Responsibilities:

• Write verification specifications, verification plans, and documentation
• Develop test benches and automate regression plans
• Understand the specifications, use cases and develop System Verilog and ‘C’ based testbenches in UVM environment and assertions
• Develop make files, Python, and Perl scripts to automate the verification tasks
• Perform complete block-level verification and contribute to the SOC chip level verification
• Be responsible for complete verifications, simulations, and debugging of verification testbenches
• Interface with cross-functional teams to understand the use cases and collaborate in all the SOC verification related activities

Requirements/Qualifications:

• Bachelors or Masters in Electrical Engineering with 0-3 years' relevant research or work experience
• Adaptability and flexibility in a fast-paced and evolving environments
• Excellent verbal and written communication skills, with the ability to convey complex technical concepts to cross-functional teams
• Proactive problem-solving attitude and a willingness to take initiative in addressing technical challenges.
• Percentage of Shift and Longest Time
  • Review/Documentation/Test planning/Meetings: 15%
  • Environment creation/test development:  40%
  • Debug, Analysis, Coverage Closure: 45%

Travel Time:

0% - 25%

Physical Attributes:

Feeling, Hearing, Other, Seeing, Talking, Works Alone, Works Around Others

Physical Requirements:

10% standing, 10% walking, 80% sitting, 100% In doors; Usual business hours.

Pay Range:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below:

Benefits of working at Microchip

The annual base salary range for this position, which could be performed in California, is $68,640 - $128,000.*

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.
For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.

To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.