EDA Tools Hardware engineer

Job Details:

Job Description: 

Defines tools, flows and methodologies of Industry standard sign-off (timing and power) for cutting edge submicron process technologies  

As an EDA Tools Hardware Engineer responsibilities include but are not limited to:

• Designs, implements, verifies, and supports the enablement and adoption of hardware sign-off tools, flows, and methodologies.
• Defines methodologies for hardware development related to technology node and EDA tool enabling.
• Develops, tests, and analyzes engineering design automation tools, flow, and methodologies to improve efficiency and optimize power and performance. Supports development and enhancement of platforms, databases, scripts, and tools flows for design automation. Builds deep understanding of digital design, verification, power and performance, clocking, and/or timing to enhance future TFM development.
• Collaborates with EDA vendors on defining and early testing of next generation design sign-off tools.
• Work closely with design teams to understand and debug static timing Analysis tool/flow/methodology issues.
• Engage with vendors to drive tool quality improvements and fixes

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:

The candidate must have Bachelor's degree in Electrical/Computer Engineering, Computer Science or related major with 3+ years experience -OR- Master's degree in Electrical/Computer Engineering, Computer Science or related major with 1+ years experience in the following:

• Static timing analysis tools, flows and methodology
• Using and debugging industry standard Static Timing Analysis tools such as Primetime, Tempus
• Using and debugging industry standard Power Analysis tools such as Primepower
• Programming in scripting languages

Preferred Qualifications:

• Good understanding of Digital Design, Backend automation flows and PPA optimization. 
• Good understanding of Static Timing Analysis and Power estimation/optimization tools. Experience using vendor tools is a plus. 
• Strong scripting/coding and problem solving skills.
• Perl, Python and TCL

 Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Job Type:College Grad

Shift:Shift 1 (United States of America)

Primary Location: US, California, Folsom

Additional Locations:US, California, Santa Clara

Business group:Product Enablement Solutions Group (PESG) is one of the key pillars, enabling Intel product design teams get to market faster with winning leadership products.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$104,890.00-$148,080.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.