Director, Physical Design

Kepler is building a new class of AI memory and logic.

Our team brings deep semiconductor expertise across the entire computing stack having pioneered numerous industry breakthroughs. We have led the development and scaling of technologies deployed across billions of chips. Additionally, our team built the world's first commercial physical synthesis tool, established foundational EDA techniques and solved long-standing challenges in ferroelectrics and beyond-CMOS devices.

At Kepler, you will work with curious, driven people solving complex technical challenges through experimentation, evidence and rapid iteration. Your work will contribute directly to the technologies we’re building and to the computing capacity they can make possible.

About the Role

We're seeking an experienced, visionary Director of Physical Design to lead full-chip and complex subsystem physical design for Kepler's cutting-edge 3D-memory-integrated AI accelerator platform. This high-impact technical leadership role drives the physical design team from netlist ingestion through GDSII signoff, working closely with architecture, RTL design, DFT, packaging and foundry teams. As the primary technical authority for physical design methodology, flow development and execution, you'll make sound VLSI trade-off decisions across power, performance, area, schedule and design quality in a fast-paced startup environment.

Key Responsibilities

• Lead full-chip physical design from netlist to GDSII signoff for complex AI accelerators, ensuring PPA and schedule goals. Drive physical design for 3D-Memory PHY Hard-IP development.

• Own floorplanning, CTS, routing, timing closure and physical verification, using industry standard tools and developing PD flows for Innovus/Genus.

• Drive team and work planning, external Design Service partners, resource allocation and milestone/quality/readiness reviews to ensure successful and timely tapeouts.

• Collaborate with SoC, DFT, Packaging, and Foundry teams to solve complex integration challenges, including 3D-memory/chiplet connectivity and power integrity.

• Develop and review power grid strategies for the compute die and 3D-memory interface; perform IR drop and electromigration (EM) analysis using Cadence Voltus or ANSYS RedHawk; account for TSV-based power delivery constraints.

• Implement scan chain routing, BIST controller placement, JTAG and boundary scan cell integration and test-mode power domain constraints in close coordination with the DFT Lead team.

• Own DRC/LVS/ERC signoff using Mentor Calibre or IC Validator; drive clean tapeout across all design blocks.

Requirements

• B.E./M.S. in Electrical Engineering, VLSI or a related discipline

• 15–20 years experience in ASIC/SoC Physical Design with a proven track record of successful silicon tapeouts.

• Expert-level proficiency in PD tools, flows and advanced process nodes (3nm/5nm/7nm).

• Mastery of CTS, timing/congestion-aware routing, SI-aware signoff and low-power/DFT design flows.

• Experience with NoC/Fabric/AXI interconnect physical implementation; placement and routing of high-performance on-chip networks.

• Experience with DFT-aware physical design; scan chain routing, BIST controller placement, JTAG/boundary scan integration and test-mode physical constraints.

• Experience with low-power physical implementation; UPF-based multi-voltage domains, power gating, retention flop placement, level shifters and isolation cells.

• Strong leadership, communication, and project management skills in fast-paced environments.

• Proven track record of multiple successful SoC productizations; from physical design through post-silicon qualification and production release.

Nice to Have

• Experience with 3D-IC, chiplets (UCIe/EMIB) or HBM base-die implementation.

• DDR/HBM PHY physical design experience.

• Strong scripting and automation skills ; Tcl (Innovus scripting), Python, Perl-for flow development, custom analysis and PD automation.

• Prior startup experience; demonstrated ability to deliver high-quality physical design results with lean teams, aggressive timelines and rapidly evolving product requirements.

Compensation and Benefits

Actual compensation will be determined based on factors including, but not limited to, relevant experience, skills, qualifications, education, job responsibilities and work location.

Kepler offers a comprehensive benefits package to eligible employees, including medical, dental and vision coverage, retirement benefits, paid time off and additional Kepler benefits as applicable. Eligibility and benefit offerings may vary based on employment status and work location.

Equal Employment Opportunity

Kepler is an Equal Opportunity Employer. We provide equal employment opportunities to all applicants and employees and do not discriminate on the basis of race, color, religion, sex, national origin, age, disability, veteran status, or any other characteristic protected under applicable federal, state, or local law.

We believe that different backgrounds, experiences, perspectives and ideas make our team stronger and help our employees, our technology and our community thrive.

Reasonable Accommodation

Kepler is committed to providing reasonable accommodations to qualified individuals with disabilities throughout the application and hiring process. If you need a reasonable accommodation to participate in the application or interview process, please contact us at 408-365-4627 or [email protected].

Fair Chance Hiring

Kepler will consider qualified applicants with criminal histories in accordance with applicable federal, state, and local laws, including the California Fair Chance Act. Applicants are not required to disclose criminal history before a conditional offer of employment except where otherwise permitted or required by applicable law.

Federal Contractor Notice

Kepler is a federal contractor or subcontractor and is committed to its obligations regarding equal employment opportunity. Kepler does not discriminate against qualified individuals on the basis of disability or protected veteran status and takes steps to employ and advance in employment qualified individuals with disabilities and protected veterans.