Director - PD STA and EMIR

Job Details:

Job Description:

We are seeking a highly experienced Director, STA & PD Closure to lead timing closure and physical design closure efforts across complex, advanced-node SoC programs. The ideal candidate brings approximately 20 years of hands-on and leadership experience in the semiconductor industry, with a strong track record of driving multiple designs through STA closure and tapeout. This is a senior technical leadership role requiring deep expertise in timing closure methodologies, cross-functional collaboration, and ownership of sign-off quality from RTL freeze through tapeout.

Key Responsibilities

• Own and drive end-to-end STA (Static Timing Analysis) and Physical Design (PD) closure for complex SoC/ASIC designs at advanced technology nodes.
• Lead timing closure strategy across multiple blocks/chips, including setup/hold analysis, clock domain crossing, multi-corner multi-mode (MCMM) sign-off, and margining.
• Drive full-chip tapeout readiness, ensuring timing, physical, and sign-off criteria are met within schedule.
• Partner closely with RTL, synthesis, place-and-route, and physical verification teams to resolve timing and physical closure bottlenecks.
• Define and continuously improve STA and PD closure methodologies, flows, and best practices across projects.
• Debug and resolve complex timing violations, including crosstalk, variation-aware timing, and advanced-node signoff challenges.
• Mentor and build a strong team of STA/PD engineers; provide technical leadership and career guidance.
• Interface with foundry/IP partners and internal stakeholders on timing and closure-related sign-off requirements.
• Report closure status, risks, and mitigation plans to senior engineering and program leadership.
• Drive root-cause analysis and process improvements to reduce closure cycle time across projects.

Qualifications:

• Approximately 20 years of relevant industry experience in semiconductor design, with a strong focus on STA and Physical Design closure.
• Deep, hands-on expertise in timing closure — including setup/hold closure, clock tree analysis, MCMM sign-off, and advanced timing exceptions.
• Demonstrated track record of having personally driven or led STA closure on multiple production designs.
• Proven tapeout experience — must have taken one or more designs successfully through to tapeout.
• Strong command of industry-standard STA and PD tools (e.g., PrimeTime, Tempus, ICC2/Innovus, or equivalent EDA tools).
• Solid understanding of physical design flows: floorplanning, placement, CTS, routing, and sign-off closure.
• Experience working at advanced process nodes and familiarity with associated signoff challenges (variation, crosstalk, EM/IR).
• Strong leadership, communication, and cross-functional collaboration skills, with prior experience managing or mentoring engineering teams.
• Bachelor's or Master's degree in Electrical/Electronics Engineering, VLSI Design, or a related field.

Preferred Attributes

• Prior experience in a Director/senior technical leadership role within an STA or PD closure organization.
• Exposure to multiple technology nodes and design types (mobile, networking, HPC, or automotive SoCs).
• Experience establishing or scaling STA/PD closure teams and processes in a growing organization.

Job Type: Regular

Shift:Shift 1 (India)

Primary Location:Bengaluru, Karnataka, India

Additional Locations:

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.