Kepler is building a new class of AI memory and logic.
Our team brings deep semiconductor expertise across the entire computing stack having pioneered numerous industry breakthroughs. We have led the development and scaling of technologies deployed across billions of chips. Additionally, our team built the world's first commercial physical synthesis tool, established foundational EDA techniques and solved long-standing challenges in ferroelectrics and beyond-CMOS devices.
At Kepler, you will work with curious, driven people solving complex technical challenges through experimentation, evidence and rapid iteration. Your work will contribute directly to the technologies we’re building and to the computing capacity they can make possible.
About the Role
We're looking for a technically deep Director, Memory Design to own the design of a custom memory controller for Kepler's cutting-edge 3D-memory-integrated AI accelerator platform. This specialized role sits at the intersection of custom DRAM architecture, digital logic design and SoC integration. You'll bring hands-on expertise in memory controller architecture and RTL design, with strong knowledge of 3D DRAM connectivity via TSV fabrics, low-latency access path design and memory subsystem optimization for AI inference. You'll both architect and implement, extending an existing memory controller to meet Kepler's custom requirements, making sound VLSI trade-offs throughout.
Key Responsibilities
Own end-to-end custom memory controller design (architecture to tapeout); architect low-latency memory access paths and optimize distributed TSV interface design.
Develop and maintain high-quality SystemVerilog RTL, perform PPA optimization and drive implementation convergence (LINT, CDC/RDC, LEC, synthesis, timing closure).
Define/review functional/formal verification plans, validate SDC timing constraints and ensure design quality through rigorous reviews.
Align with SoC architecture, physical design and post-silicon validation teams; engage with 3D DRAM partners/vendors on interface requirements.
Establish design best practices, maintain technical documentation and mentor junior engineers on 3D DRAM methodologies.
Lead the investigation and resolution of complex timing violations and structural design issues during the physical implementation phase.
Drive the definition and adoption of new design methodologies for improved power efficiency in high-bandwidth memory interfaces.
Requirements
B.Tech/M.Tech/MS/PhD in Electrical/Computer Engineering or related.
15–20 years in memory controller architecture and RTL design, including multiple successful SoC tapeouts.
Expert-level knowledge of DRAM controller design (scheduler, ECC, refresh, power management, training) and 3D memory integration (TSV connectivity, die stacking).
Proficient in SystemVerilog, SoC front-end flows (Synthesis, CDC, Formal Verification) and scripting (Python, Perl, Tcl).
Strong understanding of DRAM protocols (DDR4/5, LPDDR4/5, HBM2/3) and VLSI trade-offs (latency/bandwidth/power/area).
Experience with memory controller performance modeling (simulation, queue depth analysis, scheduler evaluation).
Proven ability to work cross-functionally and deliver complex design blocks working with small teams.
Deep hands-on experience with timing closure on complex, high-frequency digital blocks.
Proven track record of leading design teams through at least three full chip tapeout cycles in advanced process nodes (e.g., 7nm, 5nm).
Nice to have
HBM (HBM2/2E/3) base die design, custom/proprietary DRAM interface development.
Familiarity with AI/ML inference memory patterns, CXL protocols and chiplet/2.5D/3D-IC integration (interposers, multi-die power/timing).
Experience with low-power design techniques such as power gating, DVFS and multi-VT optimization.
Familiarity with industry-standard design-for-test (DFT) architectures and methodologies for high-speed memory interfaces.
Compensation and Benefits
Actual compensation will be determined based on factors including, but not limited to, relevant experience, skills, qualifications, education, job responsibilities and work location.
Kepler offers a comprehensive benefits package to eligible employees, including medical, dental and vision coverage, retirement benefits, paid time off and additional Kepler benefits as applicable. Eligibility and benefit offerings may vary based on employment status and work location.
Equal Employment Opportunity
Kepler is an Equal Opportunity Employer. We provide equal employment opportunities to all applicants and employees and do not discriminate on the basis of race, color, religion, sex, national origin, age, disability, veteran status, or any other characteristic protected under applicable federal, state, or local law.
We believe that different backgrounds, experiences, perspectives and ideas make our team stronger and help our employees, our technology and our community thrive.
Reasonable Accommodation
Kepler is committed to providing reasonable accommodations to qualified individuals with disabilities throughout the application and hiring process. If you need a reasonable accommodation to participate in the application or interview process, please contact us at 408-365-4627 or [email protected].
Fair Chance Hiring
Kepler will consider qualified applicants with criminal histories in accordance with applicable federal, state, and local laws, including the California Fair Chance Act. Applicants are not required to disclose criminal history before a conditional offer of employment except where otherwise permitted or required by applicable law.
Federal Contractor Notice
Kepler is a federal contractor or subcontractor and is committed to its obligations regarding equal employment opportunity. Kepler does not discriminate against qualified individuals on the basis of disability or protected veteran status and takes steps to employ and advance in employment qualified individuals with disabilities and protected veterans.
Skills Required
- B.Tech, M.Tech, MS, or PhD in Electrical Engineering, Electronics and Communication, Computer Engineering, or a related discipline
- 15–20 years of hands-on experience in memory controller architecture and RTL design
- Multiple successful SoC tapeouts involving complex memory subsystems
- Deep expertise in DRAM memory controller design, including scheduler architecture, command/address path, datapath, ECC, refresh, power management, and training state machines
- Experience creating or significantly modifying memory controller RTL for custom product requirements
- Understanding of DRAM timing and protocols, including DDR4/DDR5, LPDDR4/LPDDR5, HBM2/HBM3, or custom protocols
- Understanding of 3D memory integration, TSV connectivity, die stacking, signal integrity, timing, and power implications
- Hands-on experience with SoC front-end implementation flows, including LINT, CDC/RDC, LEC, synthesis, SDC constraints, and formal verification
- Ability to make VLSI trade-offs involving latency, bandwidth, area, power, scheduling, and QoS for AI accelerator workloads
- Understanding of physical design interaction, timing closure, floorplanning, power integrity, and TSV placement constraints
- Proficiency in clean, lint-free, CDC-safe, synthesis-ready SystemVerilog RTL
- Experience implementing ECC architectures such as SEC-DED, ChipKill, or custom schemes
- Strong scripting skills in Python, Perl, and Tcl
- Ability to work cross-functionally and own complex design blocks end-to-end
- Hands-on experience with HBM base-die or custom logic base-die design, PHY interaction, and TSV interface design
- Experience with custom or proprietary DRAM interface design beyond standard JEDEC protocols
- Understanding of AI/ML memory access patterns, including inference, activation memory, weight streaming, and KV-cache bandwidth
- Experience with memory controller performance modeling and bandwidth/latency simulation
- Knowledge of CXL memory protocols
- Exposure to DRAM PHY design interaction, DQ/DQS training, impedance calibration, and PHY-controller timing
- Familiarity with chiplet and 2.5D/3D-IC integration
- Experience with post-silicon memory subsystem bring-up and characterization
- Prior startup experience delivering custom silicon with lean teams and aggressive timelines
What We Do
Kepler Computing develops next-generation AI memory and logic using advanced materials, 3D architectures, ferroelectric technologies, and deep semiconductor expertise. Its products target computing’s bandwidth, capacity, energy, and density constraints, particularly for high-throughput, highly interactive AI inference. The company operates as a full-stack semiconductor technology developer spanning memory, logic, chip design, circuits, architecture, advanced packaging, and manufacturing for scalable next-generation compute systems.
