Digital verification engineer

NXP’s high performance mixed signal technologies for Automotive applications create new ways to make cars cleaner, safer, more comfortable, and more fun. NXP’s Advanced Automotive Analog (AA) Business Unit’s mission is to provide a broad portfolio of differentiated analog, mixed-signal, wireless, and energy management solutions that enable our customers to realize compelling green, safe, connected, and secure products for the automotive market.

In the APN business Unit, the Advanced Power Systems (APS) Segment drives the business of NXP’s leading power management products for automotive, industrial, and IOT markets. Together with a worldwide design team, we develop application specific standard products which integrate high performance analog functions as well as digital logic.

For our fast-growing product line we are currently looking for a candidate for a mid-level Digital Verification position to drive the digital functional verification of our mixed-signal circuit designs in automotive platforms, IOT/Consumer and/or industrial platforms. This candidate will work closely with NXP verification architect/lead and own verification if critical sub-systems on the SOC.

 The candidate will have excellent communication skills and proven ability to collaborate across organizational and geographical boundaries.

Successful applicants will be responsible for:

• Studying the specification of the device under test
• Defining the test specification in closed collaboration with design leaders, verification architect and product definers
• Work with the verification lead in defining the digital verification planning to reach 100% functional coverage prior tapeout
• Developing and/or running the UVM simulation environment (drivers, monitors, checkers and assertions) and bridge it with mixed signal verification
• Developing and/or running formal verification environment
• Developing and/or running digital and top-level simulations according to the verification plan
• Preparing and holding design verification reviews
• Creating and maintaining regression test suites
• Reporting bugs, proposing solutions and following their resolution

You will work closely with analog and digital designers as well as test and validation engineers to support both pre-silicon verification and post-silicon validation.

Working in a strong technical biased environment, you will develop your competencies and will have the opportunity of evolving in both technical or project responsibilities.

Qualifications

Required

• BS/MS in EE and 5+ years of hands-on experience on digital verification methodologies (Metrics Driven Verification, Formal)
• Strong experience writing verification plans, creating test benches and automating regression test suites, preparing and presenting detailed verification reviews
• Ability to own, execute and deliver DV coverage closure on sub-blocks or sub-systems in an IC
• Good understanding of digital RTL debug
• Working knowledge of state-of-the-art EDA tools: Cadence Xcelium, Cadence Vmanager, Cadence JasperGold
• Strong background in design and verification languages and methodologies (Verilog, SystemVerilog, UVM, SVA).
• Experience in configuration database management (DesignSync, Git, SVN)
• Solid scripting skills (Python preferred or Perl or TCL).
• Good communication skills (English)

Optional

• Experience in leading a team of DV engineers on an IC
• Experience with mixed signal (analog, digital) verification methodologies
• Experience developing behavioral models for analog IPs (both WREAL or SV RNM)
• Understand and debug analog schematics
• Tools : Cadence Virtuoso, JIRA

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