Digital Flow Enablement Solutions Architect

Reposted 16 Hours Ago
Be an Early Applicant
5 Locations
In-Office
158K-293K Annually
Expert/Leader
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
The role involves leading customer engagements in digital flow enablement, conducting design experiments, validating timing flows, and collaborating with R&D on tool improvements.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Locations: remote role but must be currently located in the US.

The position involves:

  • Leading customer engagements on standard cell library optimization and RTL->GDS enablement, including techLEF creation and updates, mapping files, and general flow development.
  • Interfacing with customers regarding digital flow enablement and methodologies, including:
    • timing characterization, including sensitivity modeling,
    • Physical view generation (LEF, GDS, abstracts, etc)
    • Logical view generation (LIB, CDL, Spectre, etc)
    • Technology LEF creation for digital tools
    • MSOA flows
  • Performing design of experiments and running Genus/Innovus to validate techLEF correctness and library performance and DRC correctness
  • Tempus timing flow development and validation
  • Working closely with R&D on tools and methodology improvements
  • Other digital P&R tasks as needed by the group
  • Processes nodes range from 1.4nm to 350nm, with majority of work at GAA advanced nodes

Position Requirements:

  • Bachelor’s degree with at least 12-16 years of design/EDA experience or Master’s degree with at least 10 years of experience. Master’s degree preferred.
  • Knowledge of standard cell and IO design, optimization and characterization methodology including LLE/LDE effects
  • Excellent digital simulation and debug skills
  • Experience with techLEF development at advanced nodes a must
  • Understanding of Liberty (.lib), Verilog & other views, such as NLDM, CCS & ECSM
  • Strong knowledge of Digital Design flows and Static Timing Analysis
  • Prior experience with ASIC digital implementation flows and EDA tools is required
  • Experience with advanced nodes (5nm and below) required.
  • Good programming knowledge in Unix, Shell scripting, perl and importantly TCL
  • Strong customer-facing communication and problem solving skills
  • Strong personal drive for continuous learning and expanding professional skill sets
  • Excellent verbal and written communication skills

Familiar with EDA tool:

  • Characterization: Liberate, Liberate MX, Liberate AMS
  • Simulators: Spectre, AMS, Xcelium
  • Digital: Genus, Innovus, Tempus, Voltus, PrimeTime etc

The annual salary range for California is $157,500 to $292,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • Bachelor's degree with at least 12-16 years of design/EDA experience or Master's degree with at least 10 years of experience
  • Knowledge of standard cell and IO design, optimization and characterization methodology
  • Experience with techLEF development at advanced nodes
  • Prior experience with ASIC digital implementation flows and EDA tools
  • Good programming knowledge in Unix, Shell scripting, Perl, and TCL

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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